Product Order Technical Tools & Support & Folder Now Documents Software Community TMS320F28035-EP SPRSP25A –JUNE 2018–REVISED JULY 2018 TMS320F28035-EP Piccolo™ Microcontroller 1 Device Overview 1.1 Features 1 • High-Efficiency 32-Bit CPU (TMS320C28x) • Code-Security Module – 60 MHz (16.67-ns Cycle Time) • 128-Bit Security Key and Lock – 16 × 16 and 32 × 32 MAC Operations – Protects Secure Memory Blocks – 16 × 16 Dual MAC – Prevents Firmware Reverse Engineering – Harvard Bus Architecture • Serial Port Peripherals – Atomic Operations – One Serial Communications Interface (SCI) – Fast Interrupt Response and Processing Universal Asynchronous Receiver/Transmitter – Unified Memory Programming Model (UART) Module – Code-Efficient (in C/C++ and Assembly) – Two Serial Peripheral Interface (SPI) Modules • Programmable Control Law Accelerator (CLA) – One Inter-Integrated-Circuit (I2C) Module – 32-Bit Floating-Point Math Accelerator – One Local Interconnect Network (LIN) Module – Executes Code Independently of the Main CPU – One Enhanced Controller Area Network (eCAN) Module • Endianness: Little Endian • Enhanced Control Peripherals • JTAG Boundary Scan Support – ePWM – IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture – High-Resolution PWM (HRPWM) • Low Cost for Both Device and System: – Enhanced Capture (eCAP) Module – Single 3.3-V Supply – High-Resolution Input Capture (HRCAP) Module – No Power Sequencing Requirement – Enhanced Quadrature Encoder Pulse (eQEP) Module – Integrated Power-On Reset and Brown-Out Reset – Analog-to-Digital Converter (ADC) – Low Power – On-Chip Temperature Sensor – No Analog Support Pins – Comparator • Clocking: • Advanced Emulation Features – Two Internal Zero-Pin Oscillators – Analysis and Breakpoint Functions – On-Chip Crystal Oscillator and External Clock – Real-Time Debug Through Hardware Input • 80-Pin PN Low-Profile Quad Flatpack (LQFP) – Watchdog Timer Module • Supports Defense, Aerospace, and Medical – Missing Clock Detection Circuitry Applications: • Up to 45 Individually Programmable, Multiplexed – Controlled Baseline GPIO Pins With Input Filtering – One Assembly/Test Site • Peripheral Interrupt Expansion (PIE) Block That – One Fabrication Site Supports All Peripheral Interrupts – Available in Extended (–55°C to 125°C) • Three 32-Bit CPU Timers Temperature Range • Independent 16-Bit Timer in Each Enhanced Pulse – Extended Product Life Cycle Width Modulator (ePWM) – Extended Product-Change Notification • On-Chip Memory – Product Traceability – Flash, SARAM, OTP, Boot ROM Available 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TMS320F28035-EP SPRSP25A –JUNE 2018–REVISED JULY 2018 www.ti.com 1.2 Applications • Appliances • Medical, Healthcare and Fitness • Building Automation • Motor Drives • Electric Vehicle/Hybrid Electric Vehicle (EV/HEV) • Power Delivery Powertrain • Telecom Infrastructure • Factory Automation • Test and Measurement • Grid Infrastructure 1.3 Description The F28035 Piccolo™ family of microcontrollers provides the power of the C28x core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency. Device Information(1) PART NUMBER PACKAGE BODY SIZE TMS320F28035MPNTEP LQFP (80) 12.0 mm × 12.0 mm (1) For more information on these devices, see Mechanical, Packaging, and Orderable Information. 2 Device Overview Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28035-EP TMS320F28035-EP www.ti.com SPRSP25A –JUNE 2018–REVISED JULY 2018 1.4 Functional Block Diagram Figure 1-1 shows the functional block diagram for the device. M0 SARAM 1K × 16 OTP 1K × 16 (0-wait) Secure M1 SARAM SARAM 1K × 16 4K/6K/8K × 16 Memory Bus (CLA Only on (0-wait) 28033 and 28035) (0-wait) Secure Code FLASH Security 16K/32K/64K × 16 Module Boot-ROM Secure 8K × 16 (0-wait) OTP/Flash PSWD Wrapper Memory Bus CLA CLA Bus TRST TCK COMP1OUT TDI GPIO COMP2OUT C28x TMS MUX COMP3OUT 32-Bit CPU TDO GPIO Mux COMP1A COMP COMP1B COMP2A COMP2B PIE 3 External Interrupts COMP3A (CLA-Accessible) COMP3B 32-Bit Peripheral Bus XCLKIN CPU Timer 0 OSC1, OSC2, X1 AIO Ext, X2 CPU Timer 1 MUX PLL, LPM Wakeup LPM, XRS CPU Timer 2 WD ADC A7:0 Memory Bus POR/ VREG B7:0 BOR 32-Bit Peripheral Bus 32-Bit Peripheral Bus 16-Bit Peripheral Bus (CLA-Accessible) eCAN SCI SPI I2C ePWM LIN eCAP eQEP HRCAP (4L FIFO) (4L FIFO) (4L FIFO) (32-mail HRPWM box) From TZx SDAx SCLx COMP1OUT, ECAPx LINATX EQE PxI LINARX EQEPxS CANTXx EQ EPxA EQ EPxB CANRXx SCITXDx SCIRXDx SPICLKx EPW MxA EPW MxB SPISTEx HRCAPx SPISIMO x SPISOMIx EPWMSYNCO COMP2OUT, EPWMSYNCI COMP3OUT GPIO MUX Copyright © 2017, Texas Instruments Incorporated A. Not all peripheral pins are available at the same time due to multiplexing. Figure 1-1. Functional Block Diagram Copyright © 2018, Texas Instruments Incorporated Device Overview 3 Submit Documentation Feedback Product Folder Links: TMS320F28035-EP TMS320F28035-EP SPRSP25A –JUNE 2018–REVISED JULY 2018 www.ti.com Table of Contents 1 Device Overview ......................................... 1 5 Detailed Description ................................... 34 1.1 Features .............................................. 1 5.1 Overview ............................................ 34 1.2 Applications........................................... 2 5.2 Memory Maps ...................................... 43 1.3 Description............................................ 2 5.3 Register Maps....................................... 47 1.4 Functional Block Diagram ............................ 3 5.4 Device Emulation Registers......................... 49 2 Revision History ......................................... 5 5.5 VREG/BOR/POR .................................... 50 3 Terminal Configuration and Functions.............. 6 5.6 System Control ...................................... 52 3.1 Pin Diagram .......................................... 6 5.7 Low-Power Modes Block............................ 60 3.2 Signal Descriptions ................................... 7 5.8 Interrupts ............................................ 61 4 Specifications ........................................... 15 5.9 Peripherals .......................................... 66 4.1 Absolute Maximum Ratings ......................... 15 6 Applications, Implementation, and Layout ...... 133 4.2 ESD Ratings ........................................ 15 6.1 TI Design or Reference Design.................... 133 4.3 Power-On Hours (POH) Limits...................... 16 7 Device and Documentation Support.............. 134 4.4 Recommended Operating Conditions............... 17 7.1 Getting Started..................................... 134 4.5 Power Consumption Summary...................... 18 7.2 Device and Development Support Tool 4.6 Electrical Characteristics ............................ 22 Nomenclature ...................................... 134 4.7 Thermal Resistance Characteristics ................ 23 7.3 Tools and Software ................................ 135 4.8 Thermal Design Considerations .................... 24 7.4 Documentation Support............................ 137 4.9 Emulator Connection Without Signal Buffering for 7.5 Community Resources............................. 138 the MCU............................................. 24 7.6 Trademarks ........................................ 138 4.10 Parameter Information .............................. 25 7.7 Electrostatic Discharge Caution ................... 139 4.11 Test Load Circuit ................................... 25 7.8 Glossary............................................ 139 4.12 Power Sequencing .................................. 26 8 Mechanical, Packaging, and Orderable 4.13 Clock Specifications ................................. 29 Information ............................................. 140 4.14 Flash Timing ........................................ 32 8.1 Packaging Information ............................. 140 4 Table of Contents Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28035-EP TMS320F28035-EP www.ti.com SPRSP25A –JUNE 2018–REVISED JULY 2018 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (June 2018) to Revision A Page • Added Operating Life Derating Chart to the Power-On Hours (POH) Limits section ...................................... 16 Copyright © 2018, Texas Instruments Incorporated Revision History 5 Submit Documentation Feedback Product Folder Links: TMS320F28035-EP TMS320F28035-EP SPRSP25A –JUNE 2018–REVISED JULY 2018 www.ti.com 3 Terminal Configuration and Functions 3.1 Pin Diagram Figure 3-1 shows the 80-pin PN Low-Profile Quad Flatpack (LQFP) pin assignments. SPISTEA TZ1 DD SS V V X1 GPIO16/SPISIMOA/TZ2 GPIO44