Imperial College London MEng Final Year Project Investigating a Heterogeneous System for Detection of Triangular Arbitrage Author: Supervisor: Jan Saganowski Prof. Wayne Luk Second Marker: Dr. David Thomas June 21, 2011 Abstract The aim of the project is to investigate the behaviour of a proposed heterogeneous system, which combines a financial modelling and an on-line component. The application scenario is the detection of triangular arbitrage opportunities in the Foreign Exchange spot market. The approach taken is to separate the problem into arbitrage detection, market data prediction and prediction checking. The constituent parts are implemented on different hardware architectures, showing interaction between the CPU and Field Programmable Gate Arrays (FPGAs). A clear relationship was found between the amount of predictions and the number of clock cycles required to execute prediction checking in hardware. This characteristic allows for straightforward adjustments to the proposed model. Furthermore, the hetero- geneous system provides a considerable reduction in latency ranging from 83% to 90% for numbers of currencies most representative of the current market size. Acknowledgements I would like to thank my supervisor, Professor Wayne Luk, for providing the inspiration for this project and his openness about which areas to investigate. Also, for his time and belief in what could be achieved. I extend my gratitude to Dr. David Thomas not only for his generous involvement, valuable advice and support throughout the course of my work but also for his suggestion to concentrate on the Foreign Exchange market. My thanks go out to Dr. Tsoi for providing help and much needed guidance regarding the AutoPilot tool. I must also acknowledge CSG, specifically Duncan White, for patience when faced with all my computing resource requests during the project. Last, but by no means least, I would like to thank my family and friends for their unwavering support and encouragement during my years at Imperial. These last few months have been challenging and I could not have made it without you. So once again, an enormous Thank You! Contents 1 Introduction 4 1.1 Foreign Exchange Market and Arbitrage . 4 1.2 Objective . 5 1.3 Report Structure and Contributions . 6 2 Background 8 2.1 Foreign Exchange Market . 8 2.1.1 Currency Pair . 9 2.1.2 Bid-Ask Spread . 9 2.2 Arbitrage . 10 2.2.1 Triangular Arbitrage . 10 2.2.2 Statistical Arbitrage . 11 2.3 Hardware Acceleration . 11 2.3.1 Field Programmable Gate Arrays . 11 2.3.2 Graphics Processing Units . 13 2.4 Related Work . 13 2.5 Summary . 15 3 Heterogeneous Model 16 3.1 Model Overview . 16 3.1.1 Market Data . 16 3.1.2 Placing Orders . 18 3.2 Model Details . 19 3.2.1 Modelling Component . 19 3.2.2 On-line Component . 20 3.3 Arbitrage Calculation . 20 3.3.1 Simple Approach . 21 3.3.2 Bid-Ask Approach . 22 3.3.3 Arbitrage Condition . 22 3.4 Selected Arbitrage Calculation . 23 3.5 Summary . 23 4 Arbitrage Detection 24 4.1 Preliminaries . 24 4.1.1 Hardware . 24 4.1.2 Compiler . 25 1 4.1.3 Environment Setup . 25 4.1.4 Run Configurations . 25 4.1.5 Timing . 26 4.2 Arbitrage Detection Algorithm . 26 4.2.1 Recursive Algorithm . 26 4.2.2 Alternative Algorithm . 27 4.2.3 Further Optimisation . 29 4.3 Multi-threading . 30 4.3.1 Two Threads . 30 4.3.2 Eight Threads . 30 4.4 Heterogeneous Model Considerations . 32 4.4.1 Single-Best Arbitrage Opportunity . 32 4.4.2 Trade Size Modification . 32 4.4.3 Threshold Modification . 34 4.5 GPU Acceleration . 36 4.6 Summary . 37 5 Market Data Prediction 38 5.1 Initial Thoughts . 38 5.2 Prediction Algorithm . 39 5.2.1 Equally Weighted . 39 5.2.2 Exponentially Weighted . 39 5.2.3 Initial Performance Measure . 41 5.3 Performance Evaluation . 42 5.3.1 Perfect Predictor . 42 5.3.2 Weighted Predictor . 43 5.3.3 Random Predictor . 43 5.3.4 Results . 43 5.4 Summary . 45 6 Prediction Checking 46 6.1 Additional Background . 46 6.1.1 AutoPilot . 47 6.1.2 Xilinx Design Flow . 47 6.1.3 Complete FPGA Implementation Run . 49 6.2 Prediction Checking Algorithm . 49 6.3 Optimisation Process . 49 6.3.1 Original Algorithm . 50 6.3.2 Memory Wrapper . 51 6.3.3 Loop Unrolling - SPRAM . 52 6.3.4 Loop Unrolling - DPRAM . 54 6.4 Compacting Data . 56 6.5 Result Space Reduction . 58 6.5.1 Single Best Prediction . 58 6.5.2 Two Best Predictions . 59 6.5.3 Further Modifications . 60 2 6.6 Evaluation Preparation . 60 6.6.1 Adjusting Predictions . 61 6.6.2 Adjusting Market Size . 61 6.6.3 Loop Unrolling . 61 6.6.4 FPGA Implementation . 61 6.7 Design Remarks . 63 6.8 Closing Remarks . 63 6.9 Summary . 64 7 Evaluation 65 7.1 Evaluation Procedure . 65 7.2 Arbitrage Detection . 66 7.2.1 Trade Size . 66 7.2.2 Threshold . 67 7.2.3 Reference CPU Implementation (Max) . 67 7.2.4 Results . 67 7.3 Data Prediction . 68 7.4 Prediction Checking . 69 7.4.1 Evaluation Runs . 69 7.4.2 Market Data Size . 71 7.4.3 Prediction Data Size . 72 7.4.4 Maximum Memory Utilisation . 73 7.4.5 Final FPGA Remarks . 74 7.5 Heterogeneous Model . 75 7.5.1 Assumptions . 75 7.5.2 Procedure . 75 7.5.3 Arbitrage Detection Extrapolation . 76 7.5.4 Prediction Checking Extrapolation . 76 7.5.5 Synchronous Model . 77 7.5.6 Asynchronous Model . 79 7.5.7 Latency . 80 7.5.8 Profit . 81 7.5.9 Final Remarks . 82 7.6 Summary . 83 8 Conclusions and Future Work 85 8.1 Conclusions ..