Actel ProASIC A3PE3000L-PQ208 Field Programmable Gate Array Single Event Effects (SEE) High-Speed Test Plan- Phase II Melanie Berg – Principle Investigator MEI HAK Kim, Mark Friendlich, Chris Perez, Christina Seidlick: MEI Ken Label: NASA/GSFC Test Dates: 9/2011 ACTEL PROASIC A3PE3000L-PQ208 FIELD PROGRAMMABLE GATE ARRAY SINGLE EVENT EFFECTS (SEE) HIGH-SPEED TEST PLAN- PHASE II .......................................................................................................... 1 MELANIE BERG – PRINCIPLE INVESTIGATOR MEI ................................................................................ 1 HAK KIM, MARK FRIENDLICH, CHRIS PEREZ, CHRISTINA SEIDLICK: MEI ............................................... 1 KEN LABEL: NASA/GSFC ..................................................................................................................... 1 1. INTRODUCTION .......................................................................................................................... 3 2. BACKGROUND ............................................................................................................................ 3 2.1 THE PROASIC3 DEVICE ARCHITECTURE AND DESIGN BUILDING BLOCKS .................................................... 3 2.2 INITIAL PHASE OF PROASIC3 HEAVY ION TESTING ................................................................................. 5 3. ANALYSIS TOOLS: NASA REAG FPGA SEU MODEL ........................................................................ 5 3.1 PCONFIGURATION ..................................................................................................................................... 6 3.2 P(FS)FUNCTIONALLOGIC ............................................................................................................................. 6 4. MITIGATION STRATEGIES ......................................................................................................... 11 5. DEVICES AND DESIGNS TESTED ................................................................................................. 13 5.1 GLOBAL ROUTES ............................................................................................................................ 14 5.2 SHIFT REGISTER ARCHITECTURES (WSRS) .......................................................................................... 14 5.2.1 Functional Description ........................................................................................................ 14 5.2.2 Combinatorial Logic and Sequential Logic Elements in the WSR ........................................ 16 5.2.3 WSR to Tester Interface ...................................................................................................... 18 5.2.4 Data Input Patterns for WSRs ............................................................................................ 19 5.2.5 WSR Output ........................................................................................................................ 19 5.2.6 WSR Expected Upsets ......................................................................................................... 20 5.3 COUNTER ARRAY ........................................................................................................................... 21 5.3.1 Counter Array Implementation .......................................................................................... 22 5.3.2 Counter I/O Interface and Expected Outputs ..................................................................... 24 5.3.3 Counter Expected Upsets .................................................................................................... 25 5.3.4 Summary of Counter Array Test Evaluations ...................................................................... 25 5.4 DSP BLOCKS ................................................................................................................................. 26 5.4.1 Process for loading ‘A’ coefficients ..................................................................................... 26 5.4.2 Process for loading ‘B’ coefficients ..................................................................................... 26 1 5.4.3 Process for loading ‘C’ coefficient ...................................................................................... 26 5.4.4 DSP I/O Interface and Expected Outputs ............................................................................ 30 5.4.5 DSP Expected Upsets .......................................................................................................... 31 5.4.6 Summary of DSP Test Evaluations ...................................................................................... 31 6. LOW COST DIGITAL TESTER (LCDT) TEST VEHICLE ...................................................................... 31 6.1 ARCHITECTURAL OVERVIEW ............................................................................................................. 32 6.1.1 I/O List and Definitions ....................................................................................................... 33 6.2 RS232 COMMUNICATION FROM THE LCDT TO THE HOST PC ................................................................ 36 6.3 RS232 COMMUNICATION FROM THE HOST PC TO THE LCDT ............................................................... 36 6.3.1 User GUI ............................................................................................................................. 36 6.3.2 User Interface and Command Control ................................................................................ 38 7. DUT TEST PROCEDURES ............................................................................................................ 40 7.1 WSR TESTING ............................................................................................................................... 40 7.1.1 Dynamic: Evaluate susceptibility of WSR ........................................................................... 40 7.2 COUNTER ARRAY TESTS .................................................................................................................. 41 7.2.1 Dynamic: Evaluate susceptibility of Counter DFF cells in biased-dynamic states ............... 41 7.3 DSP TESTS ................................................................................................................................... 41 7.3.1 Dynamic: Evaluate susceptibility of DSP Blocks in biased-dynamic states ......................... 41 7.4 RUNNING A FULL TEST .................................................................................................................... 41 7.4.1 WSR Tests ........................................................................................................................... 42 7.4.2 Counter Tests ...................................................................................................................... 42 7.4.3 DSP Tests ............................................................................................................................ 43 8. PROCESSING THE DUT OUTPUTS ............................................................................................... 43 8.1 WSR, COUNTER, H3FSM SHIFT_CLK PROCESSING ........................................................................... 43 8.2 WSR DATA PROCESSING ................................................................................................................. 44 8.2.1 WSR SEU Cross Section Calculations .................................................................................. 46 8.3 COUNTER ARRAY DATA PROCESSING ................................................................................................. 47 8.3.1 Counter Array Data Capture and compare ......................................................................... 47 8.3.2 Counter Array Error Record ................................................................................................ 47 8.3.3 Counter Array SEU Cross Section Calculations ................................................................... 48 8.4 DSP DATA PROCESSING .................................................................................................................. 49 8.4.1 DSP Block Error Record ....................................................................................................... 49 8.4.2 DSP SEU Cross Section Calculations .................................................................................... 50 9. HEAVY ION TEST FACILITY AND TEST CONDITIONS .................................................................... 50 10. HEAVY ION TEST RESULTS ....................................................................................................... 51 10.1 SINGLE EVENT LATCHUP (SEL) ....................................................................................................... 51 10.2 CONFIGURATION AND TESTING DIFFICULTIES .................................................................................... 52 10.2.1 Phase I First Test Trip 05/2010 ......................................................................................... 52 10.2.2 Phase I Second Test Trip 08/2010 .................................................................................... 52 10.2.3 Phase II Test Trip 08/2011 ................................................................................................ 52 10.2.4 Summary of Reprogramming issue .................................................................................