Circuits Lecture 11 Uniform Circuit Complexity 1 Recall 2 Recall Non-uniform complexity 2 Recall Non-uniform complexity P/1 ⊈ Decidable 2 Recall Non-uniform complexity P/1 ⊈ Decidable NP ⊆ P/log ⇒ NP = P 2 Recall Non-uniform complexity P/1 ⊈ Decidable NP ⊆ P/log ⇒ NP = P P NP ⊆ P/poly ⇒ PH = Σ2 2 Recall Non-uniform complexity P/1 ⊈ Decidable NP ⊆ P/log ⇒ NP = P P NP ⊆ P/poly ⇒ PH = Σ2 Circuit Complexity 2 Recall Non-uniform complexity P/1 ⊈ Decidable NP ⊆ P/log ⇒ NP = P P NP ⊆ P/poly ⇒ PH = Σ2 Circuit Complexity SIZE(poly) = P/poly 2 Recall Non-uniform complexity P/1 ⊈ Decidable NP ⊆ P/log ⇒ NP = P P NP ⊆ P/poly ⇒ PH = Σ2 Circuit Complexity SIZE(poly) = P/poly SIZE-hierarchy 2 Recall Non-uniform complexity P/1 ⊈ Decidable NP ⊆ P/log ⇒ NP = P P NP ⊆ P/poly ⇒ PH = Σ2 Circuit Complexity SIZE(poly) = P/poly SIZE-hierarchy SIZE(T’) ⊊ SIZE(T) if T=!(t2t) and T’=O(2t/t) 2 Recall Non-uniform complexity P/1 ⊈ Decidable NP ⊆ P/log ⇒ NP = P P NP ⊆ P/poly ⇒ PH = Σ2 Circuit Complexity SIZE(poly) = P/poly SIZE-hierarchy SIZE(T’) ⊊ SIZE(T) if T=!(t2t) and T’=O(2t/t) Most functions on t bits (that ignore last n-t bits) are in SIZE(T) but not in SIZE(T’) 2 Uniform Circuits 3 Uniform Circuits Uniform circuit family: constructed by a TM 3 Uniform Circuits Uniform circuit family: constructed by a TM Undecidable languages are undecidable for these circuits families 3 Uniform Circuits Uniform circuit family: constructed by a TM Undecidable languages are undecidable for these circuits families Can relate their complexity classes to classes defined using TMs 3 Uniform Circuits Uniform circuit family: constructed by a TM Undecidable languages are undecidable for these circuits families Can relate their complexity classes to classes defined using TMs Logspace-uniform: 3 Uniform Circuits Uniform circuit family: constructed by a TM Undecidable languages are undecidable for these circuits families Can relate their complexity classes to classes defined using TMs Logspace-uniform: An O(log n) space TM can compute the circuit 3 NCi and ACi 4 NCi and ACi NCi: class of languages decided by bounded fan-in logspace-uniform circuits of polynomial size and depth O(logi n) 4 NCi and ACi NCi: class of languages decided by bounded fan-in logspace-uniform circuits of polynomial size and depth O(logi n) ACi: Similar, but unbounded fan-in circuits 4 NCi and ACi NCi: class of languages decided by bounded fan-in logspace-uniform circuits of polynomial size and depth O(logi n) ACi: Similar, but unbounded fan-in circuits NC0 and AC0: constant depth circuits 4 NCi and ACi NCi: class of languages decided by bounded fan-in logspace-uniform circuits of polynomial size and depth O(logi n) ACi: Similar, but unbounded fan-in circuits NC0 and AC0: constant depth circuits NC0 output depends on only a constant number of input bits 4 NCi and ACi NCi: class of languages decided by bounded fan-in logspace-uniform circuits of polynomial size and depth O(logi n) ACi: Similar, but unbounded fan-in circuits NC0 and AC0: constant depth circuits NC0 output depends on only a constant number of input bits NC0 ⊊ AC0: Consider L = {1,11,111,...} 4 NC and AC 5 NC and AC i NC = ∪i>0 NC . Similarly AC. 5 NC and AC i NC = ∪i>0 NC . Similarly AC. NCi ⊆ ACi ⊆ NCi+1 5 NC and AC i NC = ∪i>0 NC . Similarly AC. NCi ⊆ ACi ⊆ NCi+1 Clearly NCi ⊆ ACi 5 NC and AC i NC = ∪i>0 NC . Similarly AC. NCi ⊆ ACi ⊆ NCi+1 Clearly NCi ⊆ ACi ACi ⊆ NCi+1 because polynomial fan-in can be reduced to constant fan-in by using a log depth tree 5 NC and AC i NC = ∪i>0 NC . Similarly AC. NCi ⊆ ACi ⊆ NCi+1 Clearly NCi ⊆ ACi ACi ⊆ NCi+1 because polynomial fan-in can be reduced to constant fan-in by using a log depth tree So NC = AC 5 NC ⊆ P 6 NC ⊆ P Generate circuit of the right input size and evaluate on input 6 NC ⊆ P Generate circuit of the right input size and evaluate on input Generating the circuit 6 NC ⊆ P Generate circuit of the right input size and evaluate on input Generating the circuit in logspace, so poly time; also circuit size is poly 6 NC ⊆ P Generate circuit of the right input size and evaluate on input Generating the circuit in logspace, so poly time; also circuit size is poly Evaluating the gates 6 NC ⊆ P Generate circuit of the right input size and evaluate on input Generating the circuit in logspace, so poly time; also circuit size is poly Evaluating the gates Poly(n) gates 6 NC ⊆ P Generate circuit of the right input size and evaluate on input Generating the circuit in logspace, so poly time; also circuit size is poly Evaluating the gates Poly(n) gates Per gate takes O(1) time + time to look up output values of (already evaluated) gates 6 NC ⊆ P Generate circuit of the right input size and evaluate on input Generating the circuit in logspace, so poly time; also circuit size is poly Evaluating the gates Poly(n) gates Per gate takes O(1) time + time to look up output values of (already evaluated) gates Open problem: Is NC = P? 6 Motivation for NC 7 Motivation for NC Fast parallel computation is (loosely) modeled as having poly many processors and taking poly-log time 7 Motivation for NC Fast parallel computation is (loosely) modeled as having poly many processors and taking poly-log time Corresponds to NC (How?) 7 Motivation for NC Fast parallel computation is (loosely) modeled as having poly many processors and taking poly-log time Corresponds to NC (How?) Depth translates to time 7 Motivation for NC Fast parallel computation is (loosely) modeled as having poly many processors and taking poly-log time Corresponds to NC (How?) Depth translates to time Total “work” is size of the circuit 7 An example 8 An example PARITY in NC1 8 An example PARITY in NC1 PARITY = { x | x has odd number of 1s } 8 An example PARITY in NC1 PARITY = { x | x has odd number of 1s } Circuit should evaluate x1⊕x2⊕...⊕xn 8 An example PARITY in NC1 PARITY = { x | x has odd number of 1s } Circuit should evaluate x1⊕x2⊕...⊕xn Tree of n-1 XOR gates: log n deep 8 An example PARITY in NC1 PARITY = { x | x has odd number of 1s } Circuit should evaluate x1⊕x2⊕...⊕xn Tree of n-1 XOR gates: log n deep Each XOR gate implemented in depth 3 8 An example PARITY in NC1 PARITY = { x | x has odd number of 1s } Circuit should evaluate x1⊕x2⊕...⊕xn Tree of n-1 XOR gates: log n deep Each XOR gate implemented in depth 3 8 Another example 9 Another example PATH ∈ AC1 9 Another example PATH ∈ AC1 “Boolean” Matrix Multiplication 9 Another example PATH ∈ AC1 “Boolean” Matrix Multiplication Z=XY: zij = ∨k=1..n (xik∧ykj) 9 Another example PATH ∈ AC1 “Boolean” Matrix Multiplication Z=XY: zij = ∨k=1..n (xik∧ykj) AC0 circuit (OR gate with fan-in n, AND gates) 9 Another example PATH ∈ AC1 “Boolean” Matrix Multiplication Z=XY: zij = ∨k=1..n (xik∧ykj) AC0 circuit (OR gate with fan-in n, AND gates) t If X adjacency matrix (with self-loops), X ij=1 iff path from i to j of length t or less 9 Another example PATH ∈ AC1 “Boolean” Matrix Multiplication Z=XY: zij = ∨k=1..n (xik∧ykj) AC0 circuit (OR gate with fan-in n, AND gates) t If X adjacency matrix (with self-loops), X ij=1 iff path from i to j of length t or less m X ij for m " n is the transitive closure 9 Another example PATH ∈ AC1 “Boolean” Matrix Multiplication Z=XY: zij = ∨k=1..n (xik∧ykj) AC0 circuit (OR gate with fan-in n, AND gates) t If X adjacency matrix (with self-loops), X ij=1 iff path from i to j of length t or less m X ij for m " n is the transitive closure n O(log n) matrix multiplications to compute X ij 9 Another example PATH ∈ AC1 “Boolean” Matrix Multiplication Z=XY: zij = ∨k=1..n (xik∧ykj) AC0 circuit (OR gate with fan-in n, AND gates) t If X adjacency matrix (with self-loops), X ij=1 iff path from i to j of length t or less m X ij for m " n is the transitive closure n O(log n) matrix multiplications to compute X ij Total depth O(log n) 9 NC1 ⊆ L 10 NC1 ⊆ L Generate circuit (implicitly) and evaluate 10 NC1 ⊆ L Generate circuit (implicitly) and evaluate cf. NC ⊆ P. But now, to conserve space, a recursive evaluation (rather than bottom-up). 10 NC1 ⊆ L Generate circuit (implicitly) and evaluate cf. NC ⊆ P. But now, to conserve space, a recursive evaluation (rather than bottom-up). For each gate, recursively evaluate each input wire 10 NC1 ⊆ L Generate circuit (implicitly) and evaluate cf. NC ⊆ P. But now, to conserve space, a recursive evaluation (rather than bottom-up). For each gate, recursively evaluate each input wire Storage: A path to the current node, from the output node: since bounded fan-in, takes O(1) bits per node; since logspace uniform that is sufficient to compute the node id in logspace 10 NC1 ⊆ L Generate circuit (implicitly) and evaluate cf.