Chapter 5: ASICs Vs. PLDs 5.1 Introduction A general definition of the term Application Specific Integrated Circuit (ASIC) is virtually every type of chip that is designed to perform a dedicated task. ASICS, more specifically, are designed by the end user to perform some proprietary application. Semi- custom and full-custom Application Specific Integrated Circuits are very useful in integrating digital, analog, mixed signal or system-on-a-chip (SOC) designs but are very costly and not schedule friendly. Depending on the design application, there are many advantages in using ASICs rather than Field Programmable Gate Arrays (FPGAs) or Complex Programmable Logic devices (CPLDs). Some advantages include higher performance, increased densities and decreased space requirements. Some disadvantages include lacking flexibility for changes and difficulty to test and debug. There are some design applications best suited for ASIC technology and others suited for PLDs. Logic designs done in FPGA occupy more space and have decreased performance and may need to be migrated to an ASIC methodology. The migration process introduces issues such as architectural difference and logic mapping to vendor specified functions. 5.2 ASIC Industry The ASIC industry is very volatile with new companies, products and methodologies emerging daily. In the mid-1980s the prediction was that ASIC designs would be taking over 50% of the electronic design market by 1990. When 1990 came the ASIC market turned out to be approximately 10%. Most of the focus for ASICS is providing a technology capable of handling 100,000 or more gates with very high performance. Most of the new ASIC designs do not require high density and 79 performance. Two-thirds of all ASIC designs fall within the 15,000 to 20,000 gate range. There are three main areas that are driving ASIC technology. The first consists of designers of high complexity segmented systems developing high performance systems on a chip. These designs typically include custom Central Processing Units (CPUs), on- chip memory, peripheral control and interface logic for end application. The other driving force behind ASIC technology is the mainstream designers that are concerned with logic consolidation and reducing the overall area that the design occupies. The last driving force is the Electronic Design Automation (EDA) tools, which are available for large complex system designs and have the flexibility to target any type of technology with a single standard design methodology. The main reason for designers to avoid ASICs is the high levels of cost and risk. Many designers do not want to use ASICs because of the concern for missing the schedule and jeopardizing the project. Projects should have contingencies in case the development of the ASIC fails either by fabrication or lack of design performance. The vast majority of design engineers have never designed an ASIC. 5.3 ASIC Advantages and Disadvantages The advantages and the disadvantages are determined by the nature of the proposed application. Factors that contribute to using ASICs are product development budget, available expertise, production volume, desired product features and competition. Sometimes there is a considerable amount of analysis required to determine if an ASIC design is appropriate and/or the application it is intended for can only be designed in an ASIC. The auto industry is concerned about cost reduction associated with large volumes 80 of a particular design. The space and military industry is concerned with the reliability and size of the design. The following is a list of ASIC advantages and disadvantages 1. ASIC Advantages • ASICS represent the only way the design may be implemented. The desired performance and functionality may not be attainable by using standard components. • ASICs can provide or incorporate unique features that may add value to a design making it more marketable. • ASICs assist in the consolidation of logic where space and size are a concern for a given application. One single ASIC can replace a number of standard components and incorporate an entire Printed Circuit Board (PCB) design. The use of ASIC technology may be able to incorporate more features into a smaller space. • ASICs, when used to reduce the amount of standard logic can decrease system costs, increase reliability and lower the power and cooling requirements. The reduction of power may allow some designs to be converted to battery operation depending on the application and end use. • Development time may be reduced for some applications if an entire system has been incorporated into a single ASIC. • ASICs provide an increase in performance and throughput when compared to standard Integrated Circuits (ICs) or PLDs. • ASICS enhance design security making it virtually impossible to reverse engineer. 81 2. ASIC Disadvantages • The cost of prototyping is quite high increasing the Nonrecurring Engineering (NRE) costs depending upon the design, complexity and method of implementation. • ASICs introduce the risk of having to do multiple iterations, which increase the cost and delays the project schedule. • It has been determined that 50% of all the ASIC designs fail on the first try to operate in the targeted system. • It is difficult to make minor changes or fine-tune the design late in the development cycle. • Testing and debugging are very difficult on an ASIC. • The ability for the design to integrate desired functions may make it not suitable for ASIC technology. • The cost of making the ASIC is extremely expensive. The increased volume reduces the overall cost of the design per unit. The volume of the design may not reach the break-even point to be cost effective compared to the use of standard components. 5.4 ASIC Design Flow The responsibilities of the development of the ASIC are shared between the ASIC vendor and the designer or user. The extent of the responsibilities, interaction between the vendor and the designer and the data that is exchanged depends on the design methodology. Figure 5.1 shows a top-level view of the basic ASIC design flow. The 82 ASIC design flow appears to be slightly more complicated than the Design flow for PLDs. ASIC VENDOR USER Design System Consultation Specification Logic Design Turnkey Test Pattern design and Generation Analysis Simulation Automatic Place Automatic Place and Route Simulation-Level Design and Route Interface Post Layout Back-annotation Approval NO Simulation Simulation File ???? YES Layout-Level Design Interface Design Verification Test Program Generation Mask Generation Wafer Fabrication NO Prototype Assembly Prototype Prototype and Test Delivery Evaluation YES Production Figure 5.1 ASIC Design Flow 83 5.5 ASIC Design Architectures There are two branches of ASIC design architecture, semi-custom and custom. Custom includes full custom and cell based, which can be broken down to standard cells and compiled cells. Semi-custom includes channeled and channel-less array-based and programmable logic devices. This section will provide a general comparison between the different types, excluding PLDs because they were discussed in Chapter 2. Figure 5.2 is an illustration of an ASIC family tree. ASIC SEMICUSTOM CUSTOM PROGRAMMABLE ARRAY- CELL-BASED FULL CUSTOM LOGIC BASED STANDARD COMPILED CELL CELL CHANNELED CHANNELESS Figure 5.2 ASIC Family Tree 5.5.1 Custom ASICs Custom ASIC designs have a wafer fabrication that is unique to a particular custom design. A semi-custom ASIC, uses predefined cell structures requiring only the interconnections to complete the design. 84 5.5.1.1 Full-Custom ASICs In a full custom design the transistors; capacitors, resistors, digital logic and analog circuits are all positioned in the circuit layout. These designs are referred to “handcrafted” designs. One key feature of this design is that it is very flexible. Each circuit element can be optimized for its particular function and the amount of silicon can be minimized. A full custom design requires designers that are highly skilled in circuit design and layout and may take many years to finish the design. The ASIC design can only be optimized for a specific target process and is not portable to other advanced processes. A full-custom design provides many advantages for a large complex design in system performance and area density. Full custom designs contribute to approximately 10% of the new designs that are being done. 5.5.1.2 Cell-Based ASICs Cell-based designs offer a compromise between full custom and array-based. Cell-based provides flexibility in circuit layout but utilizes predefined circuit elements called cells. A cell can be as simple as a resistor and as complex as a processor. The placement of a cell is not fixed to a grid like the array-based. The design process is simple because the designer does not need to know the transistor level design of each of the cells. The cells are predefined and are contained in libraries specified in the vendor’s process. The user instantiates the cell into the design, simulates the design, and gives the data base to the vendor. The Vendor will perform the automated computer-based layout. Cell-based and compiled custom designs are getting closer to the performance levels and density as full-custom. They are developed in a less amount of time and are significantly 85 lower in cost. Array-based ASICs have the major portion of the market but cell-based is closing the gap. Cell libraries can contain complex higher-level building blocks that include core microprocessors, peripheral controllers, RAM, ROM, mixed digital and analog functions and complex data path elements. Cell-based libraries are difficult to port to array-based processes. Compiled custom cells contain process-independent design methodologies. They require only a design rule check to verify that the simulation meets design requirements before they can be integrated into any process, cell-based or array-based. Cell based methodologies have higher NRE costs and have longer lead times.