Vivado Design Suite User Guide Logic Simulation UG900 (v2019.1) May 22, 2019 Revision History The following table shows the revision history for this document. Section Revision Summary 05/22/2019 Version 2019.1 General updates Updated tables 7-2, 7-3, and B-2. Functional Coverage Report Generator Added new section. xelab Command Syntax Options Updated xelab Command Syntax Options. Logic Simulation Send Feedback 2 UG900 (v2019.1) May 22, 2019 www.xilinx.com Table of Contents Revision History . 2 Chapter 1: Logic Simulation Overview Introduction . 7 Supported Simulators . 7 Simulation Flow . 8 Language and Encryption Support . 11 Chapter 2: Preparing for Simulation Overview . 12 Using Test Benches and Stimulus Files . 12 Pointing to the Simulator Install Location . 13 Compiling Simulation Libraries . 15 Using Xilinx Simulation Libraries. 19 Using Simulation Settings . 29 Adding or Creating Simulation Source Files . 34 Generating a Netlist. 36 Chapter 3: Simulating with Third-Party Simulators Introduction . 39 Running Simulation Using Third Party Simulators with Vivado IDE . 40 Dumping SAIF for Power Analysis. 43 Dumping VCD for Power Analysis. 44 Simulating IP. 46 Using a Custom DO File During an Integrated Simulation Run. 46 Running Third-Party Simulators in Batch Mode . 48 Chapter 4: Simulating with Vivado Simulator Introduction . 49 Running the Vivado Simulator . 49 Running Functional and Timing Simulation . 67 Saving Simulation Results . 71 Distinguishing Between Multiple Simulation Runs . 71 Logic Simulation Send Feedback 3 UG900 (v2019.1) May 22, 2019 www.xilinx.com Closing a Simulation. 71 Adding a Simulation Start-up Script File. 72 Viewing Simulation Messages. 73 Using the launch_simulation Command . 75 Re-running the Simulation After Design Changes (relaunch) . 76 Using the Saved Simulator User Interface Settings . 77 Chapter 5: Analyzing Simulation Waveforms with Vivado Simulator Introduction . 79 Using Wave Configurations and Windows. 79 Opening a Previously Saved Simulation Run . 81 Understanding HDL Objects in Waveform Configurations . 82 Customizing the Waveform. 85 Controlling the Waveform Display . 92 Organizing Waveforms . 96 Analyzing Waveforms . 98 Analyzing AXI Interface Transactions . 103 Chapter 6: Debugging a Design with Vivado Simulator Introduction . 118 Debugging at the Source Level . 118 Forcing Objects to Specific Values . 123 Power Analysis Using Vivado Simulator. 131 Using the report_drivers Tcl Command . 133 Using the Value Change Dump Feature . 134 Using the log_wave Tcl Command . 135 Cross Probing Signals in the Object, Wave, and Text Editor Windows . 136 Chapter 7: Simulating in Batch or Scripted Mode in Vivado Simulator Introduction . 142 Exporting Simulation Files and Scripts . 142 Running the Vivado Simulator in Batch Mode. 148 Elaborating and Generating a Design Snapshot, xelab . 151 Simulating the Design Snapshot, xsim . 162 Example of Running Vivado Simulator in Standalone Mode . 165 Project File (.prj) Syntax . 166 Predefined Macros. 167 Library Mapping File (xsim.ini) . 167 Running Simulation Modes . 168 Using Tcl Commands and Scripts . 171 Logic Simulation Send Feedback 4 UG900 (v2019.1) May 22, 2019 www.xilinx.com export_simulation . 172 export_ip_user_files . 175 Appendix A: Compilation, Elaboration, Simulation, Netlist, and.