SPI to WISHBONE Configuration Interface Bridge Usage Guide Reference Design FPGA-RD-02191-1.0 March 2020 SPI to WISHBONE Configuration Interface Bridge Usage Guide Reference Design Disclaimers Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. 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The specifications and information herein are subject to change without notice. 2 FPGA-RD-02191-1.0 SPI to WISHBONE Configuration Interface Bridge Usage Guide Reference Design Contents Acronyms in This Document ................................................................................................................................................. 5 1. Introduction .................................................................................................................................................................. 6 1.1. Quick Facts .......................................................................................................................................................... 6 1.2. Conventions ........................................................................................................................................................ 6 1.2.1. Definition of Terms ......................................................................................................................................... 6 1.2.2. Nomenclature................................................................................................................................................. 6 1.2.3. Signal Names .................................................................................................................................................. 6 2. Features ........................................................................................................................................................................ 7 3. Signal Description ......................................................................................................................................................... 8 4. Functional Overview ..................................................................................................................................................... 9 5. Design Instantiation, Simulation, and Validation ....................................................................................................... 10 5.1. EFB Generation ................................................................................................................................................. 10 5.2. IP Module Declaration and Instantiation .......................................................................................................... 11 5.3. WISHBONE Configuration Commands .............................................................................................................. 12 5.4. SPI Transmission Format] .................................................................................................................................. 15 5.5. Design Simulation.............................................................................................................................................. 16 6. Implementation .......................................................................................................................................................... 19 References .......................................................................................................................................................................... 20 Technical Support Assistance ............................................................................................................................................. 21 Revision History .................................................................................................................................................................. 22 © 2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-RD-02191-1.0 3 SPI to WISHBONE Configuration Interface Bridge Usage Guide Reference Design Figures Figure 4.1. SPI to WISHBONE Configuration Interface Bridge Functional Diagram .............................................................. 9 Figure 4.2. SPI to WISHBONE Configuration Interface Bridge Pin Diagram ........................................................................ 9 Figure 5.1. EFB Module in IPExpress ................................................................................................................................... 10 Figure 5.2. Generating an EFB Module wit IPExpress ......................................................................................................... 11 Figure 5.3. SPI Transmission Format for Write ................................................................................................................... 15 Figure 5.4. SPI Transmission Format for Read .................................................................................................................... 15 Figure 5.5. Simulation Project in Lattice Diamond ............................................................................................................. 16 Figure 5.6. Simulation Waveform for Transparent Flash Access Enable ............................................................................ 17 Figure 5.7. Simulation Waveform for Transparent Flash Access Enable ............................................................................ 18 Tables Table 1.1. Quick Facts ........................................................................................................................................................... 6 Table 3.1. Signal Description ................................................................................................................................................. 8 Table 5.1. WISHBONE Configuration Command Format .................................................................................................... 12 Table 5.2. WISHBONE Configuration Command Table ....................................................................................................... 13 Table 6.1. Performance and Resource Utilization .............................................................................................................. 19 © 2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 4 FPGA-RD-02191-1.0 SPI to WISHBONE Configuration Interface Bridge Usage Guide Reference Design Acronyms in This Document A list of acronyms used in this document. Acronym Definition FPGA Field Programmable Gate Array IP Intellectual Property LUT Lookup-Table SPI Serial Peripheral Interface WB WISHBONE Bus SDA Serial Data SCL Serial Clock NVM Non-Volatile Memory (NVCM for MachXO3L, Flash memory for others) SDM Self-Download Mode GPIO General Purpose Input/Output EFB Embedded Function Block © 2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-RD-02191-1.0 5 SPI to WISHBONE Configuration Interface Bridge Usage Guide Reference Design 1. Introduction The SPI to WISHBONE Configuration Interface Bridge Reference Design provides a Slave SPI interface with bridging logic to convert the SPI traffic into WISHBONE bus format. Hence, this allows the external SPI master to access Lattice FPGA configuration logic through the internal fabric WISHBONE interface, which exists on the MachXO2™, MachXO3™, and MachXO3D™ device families. This IP can serve as a replacement for the Slave SPI sysConfig™ interface and provide flexibility to the SPI interface from any available