Playstation Emulation Guide Lionel Flandrin October 20, 2016 1 Contents 1 Introduction 6 1.1 Isn't emulation complicated? . .6 1.2 Feedback . .6 2 The CPU: Instructions and the memory 6 2.1 What is a CPU, anyway? . .6 2.2 Architecture . .7 2.3 The code . .7 2.4 The Program Counter register . .7 2.4.1 Reset value of the PC . .9 2.5 The Playstation memory map . .9 2.5.1 Implementing the memory map . 10 2.6 The BIOS . 10 2.7 Loading the BIOS . 11 2.8 The interconnect . 12 2.9 Gluing the interconnect to the CPU . 14 2.10 Instruction decoding . 16 2.11 General purpose registers . 17 2.11.1 The $zero register . 18 2.11.2 The $ra register . 18 2.12 Special purpose registers . 18 2.13 Implementing the general purpose registers . 19 2.14 LUI instruction . 20 2.15 ORI instruction . 20 2.16 Writing to memory . 21 2.16.1 Unaligned memory access . 22 2.16.2 Expansion mapping . 23 2.17 Sign extension . 23 2.18 SW instruction . 25 2.19 SLL instruction . 25 2.20 ADDIU instruction . 27 2.21 RAM configuration register . 28 2.22 J instruction . 28 2.23 Branch delay slots . 29 2.24 OR instruction . 30 2.25 Type safety in the register interface . 31 2.26 CACHE CONTROL register . 32 2.27 The coprocessors . 32 2.28 MTC0 instruction . 33 2.29 BNE instruction . 34 2.30 ADDI instruction . 35 2.31 Memory loads . 36 2.32 Load delay slots . 37 2.33 LW instruction . 39 2.34 The RAM . 40 2.35 The coprocessor 0 registers . 41 2.36 SLTU instruction . 42 2.37 ADDU instruction . 42 2 2.38 Regions . 43 2.39 SH instruction . 44 2.40 SPU registers . 45 2.41 JAL instruction . 46 2.42 ANDI instruction . 47 2.43 SB instruction . 47 2.44 Expansion 2 . 48 2.45 JR instruction . 48 2.46 LB instruction . 48 2.47 BEQ instruction . 50 2.48 Expansion 1 . 50 2.49 RAM byte access . 51 2.50 MFC0 instruction . 51 2.51 AND instruction . 52 2.52 ADD instruction . 52 2.53 Interrupt Control registers . 53 2.54 BGTZ instruction . 54 2.55 BLEZ instruction . 54 2.56 LBU instruction . 55 2.57 JALR instruction . 55 2.58 BLTZ, BLTZAL, BGEZ and BGEZAL instructions . 55 2.59 SLTI instruction . 57 2.60 SUBU instruction . 57 2.61 SRA instruction . 57 2.62 DIV instruction . 58 2.63 MFLO instruction . 60 2.64 SRL instruction . 60 2.65 SLTIU instruction . 61 2.66 DIVU instruction . 61 2.67 MFHI instruction . 62 2.68 SLT instruction . 62 2.69 Interrupt Control read . 62 2.70 Timer registers . 63 2.71 Exceptions . 63 2.72 SYSCALL instruction . 66 2.73 MTLO instruction . 67 2.74 MTHI instruction . 68 2.75 RFE intsruction . 68 2.76 Exceptions and branch delay slots . 69 2.77 ADD and ADDI overflows . 71 2.78 Store and load alignment exceptions . 72 2.79 PC alignment exception . 73 2.80 RAM 16bit store . 73 2.81 DMA registers . 74 2.82 LHU instruction . 75 2.83 SLLV instruction . 76 2.84 LH instruction . 77 2.85 NOR instruction . 77 2.86 SRAV instruction . 78 2.87 SRLV instruction . 78 3 2.88 MULTU instruction . 79 2.89 GPU registers . 79 2.89.1 GP0: Draw Mode Setting command . 80 2.90 Interrupt Control 16bit access . 81 2.91 Timer registers 32bit access . 81 2.92 GPUSTAT \DMA ready" field . 82 2.93 XOR instruction . 83 2.94 BREAK instructions . 83 2.95 MULT instruction . 84 2.96 SUB instruction . 84 2.97 XORI instruction . 85 2.98 Cop1, cop2 and cop3 opcodes . 85 2.99 Non-aligned reads . 86 2.99.1 LWL instruction . 87 2.99.2 LWR instruction . 88 2.100Non-aligned writes . 89 2.100.1 SWL instruction . 89 2.100.2 SWR instruction . 89 2.101Coprocessor loads and stores . 90 2.101.1 LWCn instructions . 90 2.101.2 SWCn instructions . 91 2.102Illegal instructions . 91 3 The DMA: Ordering tables and the GPU 93 3.1 DMA Control register . 94 3.2 DMA Interrupt register . 96 3.3 DMA Channel Control register . 97 3.4 DMA Base Address register . 102 3.5 DMA Block Control register . ..