A Distributed Fair Queuing MAC Scheduler for Wireless ATM Network Wing-Chung Hung A thesis submitted in conforrnity with the requirements for the degree of Master of Applied Science Graduate Department of Electrical and Cornputer Engineering University of Toronto O Copyright by Wing-Chung Hung 1997 395 Wellington Street 395, rue Wellington Ottawa ON K1A ON4 Ottawa ON K1A ON4 Canada Canada Your fi& Votre référence Our file Norre réldrence The author has granted a non- L'auteur a accordé une licence non exclusive licence allowing the exclusive permettant à la National Library of Canada to Bibliothéque nationale du Canada de reproduce, loan, distribute or sel1 reproduire, prêter, distribuer ou copies of this thesis in microform, vendre des copies de cette thèse sous paper or electronic formats. la forme de microfiche/fïlm, de reproduction sur papier ou sur format électronique. The author retains ownership of the L'auteur conserve la propriété du copyright in this thesis. Neither the droit d'auteur qui protège cette thèse. thesis nor substantial extracts from it Ni la thèse ni des extraits substantiels may be printed or otherwise de celle-ci ne doivent être imprimés reproduced without the author's ou autrement reproduits sans son permission. autorisation. Scheduler for Wireless ATM Network WingChung Hung Master of Applied Science, 1997 Graduate Department of Electrical and Computer Engineering University of Toronto Abstract A centraiized wireless ATM LAN consists of a base station and multiple mobile stations. Since they share one cornrnon transmission medium, medium access control (MAC) is needed to coordinate the order of transmission. To maintain features of BISDN, the MAC has to consider a connection's Quality of Service while ailocating resources. One of the proposed MAC protocols for providing wireless multiservices is called distributed fair queuing (DFQ). DFQ is a TDMA-based MAC scheme which dynamically performs per-ceïi scheduling based on the celi's priority. Success of implementing DFQ largely depends on scheduluig efficiency. A software scheduler wili not be fast enough for this real time task. Therefore, an efficient hardware scheduler is required. The major theme of this thesis is to design such a scheduler. As a second theme, it considers issues of WATM LAN system design and proposes a system architecture for implernenting MAC functions using existing commercial ATM cards. I would like to thank my supervisor Prof. Leon-Garcia for providing guidance on the research direction and providing assistance, suggestions and consultation for problems throughout the research. 1 would also like to thank many fellow students in the Communication Group who provided valuable assistance in various ways: Richard Kautz and Seyed Mohammed Ali Arad, who workeci on the same project, provided many materials and references on the wireless ATM; Massoud Reza Hashemi had many inputs on the design of the wrap sequencer; Massoud Hadjiahmad provided much information on hardware parts suitable to be used in building our MAC board; Keith Chow provides information on the ATM products. 1 would also like to thank Prof. Paul Chow and his student Vineet Joshi for implementing and testing the Wrap Sequencer in their FPGA board. iii Abstract ................................................................................................................ ii Acknowledgment .................................................................................................. iii List of Tables ........................................................................................................ vi List of Figures ....................................................................................................... vii List of Acronyms ............................................................................................. viii 1 . Introduction ...................................................................................................... 1.1. Thesis Background ............................................................................ 1.2. Project Background ........................................................................... 1.3. Thesis Organization ........................................................................... 2. ATM and Wireless ATM ................................................................................. 2.1. ATM Network .................................................................................... 2.1.1. ATM Adaptation Layer and Services .................................. 2.1.2. ATM Layer ......................................................................... 2.1.3. Physical Layer ..................................................................... 2.1.4. ATM Cell ............................................................................ 2.1.5. ATM QoS Enforcement ...................................................... 2.2. Wireless ATM ................................................................................... 2.2.1 . WATM Reference Model ................................................... 2.2.2. WATM LAN Topology ...................................................... 2.2.3. QoS of WATM Services ..................................................... 2.2.4. Distributed Fair Queuing (DFQ) ........................................ 2.2.5. Scheduler in DFQ System .................................................... 3. Virtual Time Bounding ...................................................................................... 3.1. Leaky Bucket Flow Control ............................................................... 3.2. Virtual Finish Time Bounding ........................................................... 3.2.1. General Process Sharing and DFQ ..................................... 3.2.2. GPS Maximum Backlog ..................................................... 3.2.3. GPS Virtual Time ............................................................... 3.2.4. SCFQ Virtual Time ............................................................. 3.3. VirtuaI Time Granularity .................................................................... 3.4. v muai 1 ime Bwunuing ror ury scneauler ....................................... 3.5. Summary .......................................................................................... 4 . Wrap Sequencer .............................................................................................. 4.1. Generic Sequencer and Wrap Sequencer ........................................... 4.2. Key (Virtual Time) Wrap Around Problem ....................................... 4.3. Solutions to the Key Wrap-Around Problem ..................................... 4.3.1 Key Rotation Algorithm ...................................................... 4.4. Wrap Sequencer and Key Rotation Aigorithm ................................... 4.4.1 Wrap Sequencer Design ...................................................... 4.5. Wrap Sequencer Synchronization ..................................................... 4.6. Wrap Sequencer Components and Operation .................................... 4.6.1. Wrap Sequencer Entities .................................................... 4.6.2. Source-Sink Switching ....................................................... 4.6.3. Key Rotation ...................................................................... 4.6.4. Source Blocking ................................................................. 4.6.4.1. Global Blocking Signals ....................................... 4.6.4.2. Local Blocking Signals ........................................ 4.7. Sequencing Elements ........................................................................ 4.7.1. An Example ....................................................................... 4.7.2. Sequencing Elements in General ........................................ 4.8. Size of Sequencer ............................................................................. 4.9. Summary of Features of Wrap Sequencer ......................................... 5 . DFQ Scheduler ............................................................................................... 5.1. DFQ Scheduler for WATM MAC Scheduling ................................... 5.2. DFQ Scheduler ................................................................................. 5.2.1. Receive FIFO and Gate Controller ..................................... 5.2.2. Recycle FIFO. Recycle Controller and Wrap Sequencer ..... 5.2.3. Sequencer-FIFO In terface .................................................. 5.3. Scheduler Parameter and Performance .............................................. 5.3.1. Parameter of Recycle FIFO and Wrap Sequencer ............... 5.4. Cascade Schedulers .......................................................................... 5.5. Summary .......................................................................................... 6. Wireless ATM Bridge ..................................................................................... .... .,................................................................................................. JY 6.2. Advantages of the "Decomposed" Mode1 ........................................ 53 6.3. WATM Bridge Components ......................................................... 54 6.3.1.ATMAdapter ................................................................. 55 6.3.2.MACBoard ......................................................................... 55 6.3.3. Part List .........................................................................