TMS320C62x DSP CPU and Instruction Set Reference Guide Literature Number: SPRU731A May 2010 ii Preface Read This First About This Manual The TMS320C6000™ digital signal processor (DSP) platform is part of the TMS320™ DSP family. The TMS320C62x™ DSP generation and the TMS320C64x™ DSP generation comprise fixed-point devices in the C6000™ DSP platform, and the TMS320C67x™ DSP generation comprises floating- point devices in the C6000 DSP platform. The C62x™ and C64x™ DSPs are code-compatible. This document describes the CPU architecture, pipeline, instruction set, and interrupts of the C62x DSP. Notational Conventions This document uses the following conventions. - Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. Related Documentation From Texas Instruments The following documents describe the C6000™ devices and related support tools. Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com. The current documentation that describes the C6000 devices, related periph- erals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000. TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) describes the peripherals available on the TMS320C6000™ DSPs. TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the TMS320C62x™ and TMS320C67x™ DSPs, develop- ment tools, and third-party support. TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and assembly code for the TMS320C6000™ DSPs and includes application program examples. SPRU731A Read This First iii TrademarksRelated Documentation From Texas Instruments / Trademarks TMS320C6000 Chip Support Library API Reference Guide (literature number SPRU401) describes a set of application programming interfaces (APIs) used to configure and control the on-chip peripherals. Trademarks Code Composer Studio, C6000, C62x, C64x, C67x, TMS320C2000, TMS320C5000, TMS320C6000, TMS320C62x, TMS320C64x, TMS320C67x, and VelociTI are trademarks of Texas Instruments. Trademarks are the property of their respective owners. iv Read This First SPRU731A Contents Contents 1 Introduction .................................................................... 1-1 Provides features and options of the TMS320C62x DSP. An overview of the DSP architecture is also provided. 1.1 TMS320 DSP Family Overview.............................................. 1-2 1.2 TMS320C6000 DSP Family Overview........................................ 1-2 1.3 TMS320C62x DSP Features and Options..................................... 1-4 1.4 TMS320C62x DSP Architecture.............................................. 1-6 1.4.1 Central Processing Unit (CPU)....................................... 1-7 1.4.2 Internal Memory.................................................... 1-7 1.4.3 Memory and Peripheral Options...................................... 1-7 2 CPU Data Paths and Control.................................................... 2-1 Provides information about the data paths and control registers. The two register files and the data cross paths are described. 2.1 Introduction ............................................................... 2-2 2.2 General-Purpose Register Files.............................................. 2-2 2.3 Functional Units........................................................... 2-5 2.4 Register File Cross Paths................................................... 2-6 2.5 Memory, Load, and Store Paths.............................................. 2-6 2.6 Data Address Paths........................................................ 2-7 2.7 Control Register File....................................................... 2-7 2.7.1 Register Addresses for Accessing the Control Registers................. 2-8 2.7.2 Pipeline/Timing of Control Register Accesses........................... 2-9 2.7.3 Addressing Mode Register (AMR).................................... 2-10 2.7.4 Control Status Register (CSR)....................................... 2-13 2.7.5 Interrupt Clear Register (ICR)....................................... 2-16 2.7.6 Interrupt Enable Register (IER)...................................... 2-17 2.7.7 Interrupt Flag Register (IFR)......................................... 2-18 2.7.8 Interrupt Return Pointer Register (IRP)............................... 2-19 2.7.9 Interrupt Set Register (ISR)......................................... 2-20 2.7.10 Interrupt Service Table Pointer Register (ISTP)........................ 2-21 2.7.11 Nonmaskable Interrupt (NMI) Return Pointer Register (NRP)............ 2-22 2.7.12 E1 Phase Program Counter (PCE1).................................. 2-22 SPRU731A Contents v Contents 3 Instruction Set .................................................................. 3-1 Describes the assembly language instructions of the TMS320C62x DSP. Also described are parallel operations, conditional operations, resource constraints, and addressing modes. 3.1 Instruction Operation and Execution Notations................................. 3-2 3.2 Instruction Syntax and Opcode Notations..................................... 3-5 3.3 Delay Slots ............................................................... 3-6 3.4 Parallel Operations......................................................... 3-7 3.4.1 Example Parallel Code.............................................. 3-9 3.4.2 Branching Into the Middle of an Execute Packet......................... 3-9 3.5 Conditional Operations.................................................... 3-10 3.6 Resource Constraints..................................................... 3-11 3.6.1 Constraints on Instructions Using the Same Functional Unit............. 3-11 3.6.2 Constraints on Cross Paths (1X and 2X).............................. 3-11 3.6.3 Constraints on Loads and Stores.................................... 3-12 3.6.4 Constraints on Long (40-Bit) Data.................................... 3-13 3.6.5 Constraints on Register Reads...................................... 3-14 3.6.6 Constraints on Register Writes...................................... 3-15 3.7 Addressing Modes........................................................ 3-16 3.7.1 Linear Addressing Mode............................................ 3-16 3.7.2 Circular Addressing Mode.......................................... 3-17 3.7.3 Syntax for Load/Store Address Generation............................ 3-18 3.8 Instruction Compatibility................................................... 3-20 3.9 Instruction Descriptions.................................................... 3-20 ABS (Absolute Value With Saturation)....................................... 3-24 ADD (Add Two Signed Integers Without Saturation)........................... 3-26 ADDAB (Add Using Byte Addressing Mode).................................. 3-30 ADDAH (Add Using Halfword Addressing Mode).............................. 3-32 ADDAW (Add Using Word Addressing Mode)................................. 3-34 ADDK (Add Signed 16-Bit Constant to Register).............................. 3-36 ADDU (Add Two Unsigned Integers Without Saturation)........................ 3-37 ADD2 (Add Two 16-Bit Integers on Upper and Lower Register Halves)........... 3-39 AND (Bitwise AND)....................................................... 3-41 B (Branch Using a Displacement)........................................... 3-43 B (Branch Using a Register)................................................ 3-45 B IRP (Branch Using an Interrupt Return Pointer)............................. 3-47 B NRP (Branch Using NMI Return Pointer)................................... 3-49 CLR (Clear a Bit Field)..................................................... 3-51 CMPEQ (Compare for Equality, Signed Integers).............................. 3-54 CMPGT (Compare for Greater Than, Signed Integers)......................... 3-56 CMPGTU (Compare for Greater Than, Unsigned Integers)..................... 3-59 CMPLT (Compare for Less Than, Signed Integers)............................ 3-61 CMPLTU (Compare for Less Than, Unsigned Integers)........................ 3-64 EXT (Extract and Sign-Extend a Bit Field).................................... 3-66 EXTU (Extract and Zero-Extend a Bit Field).................................. 3-69 vi Contents SPRU731A Contents IDLE (Multicycle NOP With No Termination Until Interrupt)...................... 3-72 LDB(U) (Load Byte From Memory With a 5-Bit Unsigned Constant Offset or Register Offset)................................................. 3-73 LDB(U) (Load Byte From Memory With a 15-Bit Unsigned Constant Offset)....... 3-76 LDH(U) (Load Halfword From Memory With a 5-Bit Unsigned Constant Offset or Register Offset)................................................. 3-78 LDH(U) (Load Halfword From Memory With a 15-Bit Unsigned Constant Offset)... 3-81 LDW (Load Word From Memory With a 5-Bit Unsigned Constant Offset or Register Offset)................................................. 3-83 LDW (Load Word From Memory With a 15-Bit Unsigned Constant Offset)........ 3-86 LMBD (Leftmost Bit Detection).............................................. 3-88 MPY (Multiply Signed 16 LSB by Signed 16 LSB)............................. 3-90 MPYH (Multiply Signed 16 MSB by Signed 16 MSB)........................... 3-92 MPYHL (Multiply Signed 16 MSB by Signed 16 LSB).......................... 3-93 MPYHLU (Multiply Unsigned 16 MSB by Unsigned