Overview Historically, the limiting factor in a computer’s performance has been memory access time – Memory speed has been slow compared to the speed of the processor EE 4504 – A process could be bottlenecked by the memory Computer Organization system’s inability to “keep up” with the processor Our goal in this section is to study the development of an effective memory Section 3 organization that supports the processing Computer Memory power of the CPU – General memory organization and performance – “Internal” memory components and their use – “External” memory components and their use Reading: Text, chapters 4 and 5 EE 4504 Section 3 1 EE 4504 Section 3 2 1 Terminology Capacity: the amount of information that Access time: can be contained in a memory unit -- – For RAM, the time to address the unit and usually in terms of words or bytes perform the transfer Word: the natural unit of organization in – For non-random access memory, the time to position the R/W head over the desired location the memory, typically the number of bits used to represent a number Memory cycle time: Access time plus any other time required before a second access Addressable unit: the fundamental data can be started element size that can be addressed in the memory -- typically either the word size or Access technique: how are memory individual bytes contents accessed – Random access: Unit of transfer: The number of data » Each location has a unique physical address elements transferred at a time -- usually » Locations can be accessed in any order and bits in main memory and blocks in all access times are the same secondary memory » What we term “RAM” is more aptly called Transfer rate: Rate at which data is read/write memory since this access transferred to/from the memory device technique also applies to ROMs as well » Example: main memory EE 4504 Section 3 3 EE 4504 Section 3 4 2 – Sequential access: – Associative access: » Data does not have a unique address » A variation of random access memory » Must read all data items in sequence until » Data items are accessed based on their the desired item is found contents rather than their actual location » Access times are highly variable » Search all data items in parallel for a match » Example: tape drive units to a given search pattern – Direct access: » All memory locations searched in parallel » Data items have unique addresses without regard to the size of the memory » Access is done using a combination of Extremely fast for large memory sizes moving to a general memory “area” » Cost per bit is 5-10 times that of a “normal” followed by a sequential access to reach the RAM cell desired data item » Example: some cache memory units » Example: disk drives EE 4504 Section 3 5 EE 4504 Section 3 6 3 Memory Hierarchy Major design objective of any memory Basis of the memory hierarchy system – Registers internal to the CPU for temporary – To provide adequate storage capacity at data storage (small in number but very fast) – An acceptable level of performance – External storage for data and programs – At a reasonable cost (relatively large and fast) – External permanent storage (much larger and Four interrelated ways to meet this goal much slower) – Use a hierarchy of storage devices Characteristics of the memory hierarchy – Develop automatic space allocation methods for efficient use of the memory – Consists of distinct “levels” of memory components – Through the use of virtual memory techniques, free the user from memory management tasks – Each level characterized by its size, access time, and cost per bit – Design the memory and its related interconnection structure so that the processor – Each increasing level in the hierarchy consists can operate at or near its maximum rate of modules of larger capacity, slower access time, and lower cost/bit Goal of the memory hierarchy – Try to match the processor speed with the rate of information transfer from the lowest element in the hierarchy EE 4504 Section 3 7 EE 4504 Section 3 8 4 Memory Technology Size Access Type Time Registers Cache Semiconductor 128-512 10 ns in the CPU RAM KB Cache Main Semiconductor 4-128 MB 50 ns Memory RAM Main memory Magnetic Hard Disk Gigabyte 10 ms, Disk 10 MB/sec Disk cache Optical Disk CD-ROM Gigabyte 300 ms, 600 KB/sec Magnetic disk Magnetic Tape 100s MB Sec-min., Optical disk Magnetic tape Tape 10MB/min Typical memory Parameters The memory hierarchy EE 4504 Section 3 9 EE 4504 Section 3 10 5 The memory hierarchy works because of Example: locality of reference – Two-level memory system – Memory references made by the processor, for – Level 1 access time of 1 us both instructions and data, tend to cluster – Level 2 access time of 10us together – Ave access time = H(1) + (1-H)(10) us » Instruction loops, subroutines » Data arrays, tables – Keep these clusters in high speed memory to reduce the average delay in accessing data – Over time, the clusters being referenced will change -- memory management must deal with this Figure 4.2 2-level memory performance EE 4504 Section 3 11 EE 4504 Section 3 12 6 Main Memory Core memory Semiconductor memory – Used in generations 2 and 3 – Typically random access – Magnetic cores (toroids) used to store logical 0 – RAM: actually read-write memory or 1 state by inducing an E-field in them » Dynamic RAM (hysteresis loop) Storage cell is essentially a transistor » 1 core = 1 bit of storage acting as a capacitor – Required addressing and sensing wires ran Capacitor charge dissipates over time through each core causing a 1 to flip to a zero – Destructive readout Cells must be refreshed periodically to – Obsolete avoid this » Replaced in the 1970s by semiconductor Very high packaging density memory » Static RAM: basically an array of flip-flop storage cells Uses 5-10x more transistors than similar dynamic cell so packaging density is 10x lower Faster than a dynamic cell EE 4504 Section 3 13 EE 4504 Section 3 14 7 – Read Only Memories (ROM) » EEPROMS » “Permanent” data storage Electrically erasable PROMs » ROMs Can be written to many times while Data is “wired in” during fabrication at remaining in a system a chip manufacturer’s plant Does not have to be erased first Purchased in lots of 10k or more Program individual bytes » PROMs Writes require several hundred usec per Programmable ROM byte Data can be written once by the user Used in systems for development, employing a PROM programmer personalization, and other tasks Useful for small production runs requiring unique information to be stored » EPROM » Flash Memory Erasable PROM Similar to EEPROM in using electrical Programming is similar to a PROM erase Can be erased by exposing to UV light Fast erasures, block erasures Higher density than EEPROM EE 4504 Section 3 15 EE 4504 Section 3 16 8 – Organization » Each memory chip contains a number of 1- bit cells 1, 4, and 16 million cell chips are common » Cells can be arranged as a single bit column (e.g., 4Mx1) or in multiple bits per address location (e.g., 1Mx4) » To reduce pin count, address lines can be multiplexed with data and/or as high and low halves Trade off is in slower operation » Typical control lines W* (write), OE* (output enable) for write and read operations CS* (chip select) derived from external address decoding logic RAS*, CAS* (row and column address selects) used when address is applied to the chip in 2 halves Figure 4.8 256Kx8 memory from 256Kx1 chips EE 4504 Section 3 17 EE 4504 Section 3 18 9 – Improvements to DRAM » Basic DRAM design has not changed much since its development in the 70s » Cache was introduced to improve performance Limited to no gain in performance after a certain amount of cache is implemented » Enhanced DRAM Add fast 1-line SRAM cache to DRAM chip Consecutive reads to the same line are from this cache and thus faster than the DRAM itself Tests indicate these chips can perform as well as tradition DRAM-cache combinations » Cache DRAM Figure 4.9 1Mx8 memory from 256Kx1 chips Use larger SRAM cache on the chip as a true multi-line cache Use it as a serial data stream buffer for EE 4504 Section 3 19 EE 4504 Section 3 block data transfers 20 10 Error Correction Semiconductor memories are subject to errors – Hard (permanent) errors » Environmental abuse » Manufacturing defects » Wear – Soft (transient) errors » Power supply problems » Alpha particles Problematic as feature sizes shrink – Memory systems include logic to detect and/or correct errors » Width of memory word is increased » Additional bits are parity bits Figure 4.10 Basic error detection and correction circuitry » Number of parity bits required depends on the level of detection and correction needed EE 4504 Section 3 21 EE 4504 Section 3 22 11 General error detection and correction Single error detection and correction – A single error is a bit flip -- multiple bit flips – For each valid codeword, there will be 2K-1 can occur in a word invalid codewords – 2M valid data words – 2K-1 must be large enough to identify which of – 2M+K codeword combinations in the memory the M+K bit positions is in error – Distribute the 2M valid data words among the – Therefore 2K-1 > M+K 2 M+K codeword combinations such that the » 8-bit data, 4 check bits “distance” between valid words is sufficient to » 32-bit data, 6 check bits distinguish the error – Arrange bits as shown in Figure 4.12 Valid codeword 1 bit flip between each codeword 7 bit flips would map the upper valid codeword into the lower one Detect up to 6 errors, Valid codeword Correct up to 3 errors EE 4504 Section 3 23 EE 4504 Section 3 24 12 Cache Memory –