Epiphany Architecture Reference Table of Contents 1 Introduction ......................................................................................................................... 10 2 Programming Model ........................................................................................................... 13 2.1 Programming Model Introduction ................................................................................................. 13 2.2 Parallel Programming Example ..................................................................................................... 14 3 Software Development Environment ................................................................................ 16 4 Memory Architecture ......................................................................................................... 17 4.1 Memory Address Map.................................................................................................................... 17 4.2 Memory Order Model .................................................................................................................... 19 4.3 Endianness ..................................................................................................................................... 20 4.4 Load/Store Alignment Restrictions ................................................................................................ 21 4.5 Program-Fetch Alignment Restrictions .......................................................................................... 21 5 eMesh Network-On-Chip ................................................................................................... 22 5.1 Network Topology ......................................................................................................................... 22 5.2 Routing Protocol ............................................................................................................................ 24 5.3 Read Transactions .......................................................................................................................... 25 5.4 Direct Inter-Core Communication ................................................................................................. 26 5.5 Arbitration Scheme ........................................................................................................................ 27 5.6 Data Sizes and Alignment .............................................................................................................. 27 5.7 Multicast Routing .......................................................................................................................... 28 5.8 Detour Routing Support ................................................................................................................. 28 6 Processor Node Subsystem ................................................................................................. 29 6.1 Processor Node Overview .............................................................................................................. 29 6.2 Mesh-Node Crossbar Switch ......................................................................................................... 31 6.3 Mesh-Node Arbitration .................................................................................................................. 33 7 eCore CPU ........................................................................................................................... 34 7.1 Overview ........................................................................................................................................ 34 7.2 Data Types ..................................................................................................................................... 37 7.3 Local Memory Map ....................................................................................................................... 40 7.4 General Purpose Registers ............................................................................................................. 40 7.5 Status Flags .................................................................................................................................... 43 7.6 The Epiphany Instruction Set ......................................................................................................... 46 7.7 Pipeline Description ....................................................................................................................... 57 7.8 Interrupt Controller ........................................................................................................................ 63 7.8.1 Overview ................................................................................................................................................... 63 7.8.2 Global Interrupt Disable Flag (GID) ........................................................................................................... 65 7.8.3 User Interrupts ......................................................................................................................................... 65 7.8.4 Interrupt Latency ...................................................................................................................................... 66 7.9 Hardware Loops (LABS) ............................................................................................................... 67 7.10 Debug Unit ..................................................................................................................................... 68 2 Copyright 2008-2013 Adapteva. All rights reserved REV 14.03.11 8 Direct Memory Access (DMA) ........................................................................................... 69 8.1 Overview ........................................................................................................................................ 69 8.2 DMA Descriptors ........................................................................................................................... 71 8.3 DMA Channel Arbitration .............................................................................................................. 71 8.4 DMA Usage Restrictions ............................................................................................................... 71 8.5 DMA Transfer Examples ............................................................................................................... 72 9 Event Timers ....................................................................................................................... 73 10 Memory Protection Unit (LABS) ...................................................................................... 74 Appendix A: Instruction Set Reference .................................................................................... 75 ADD ............................................................................................................................................................ 76 AND ............................................................................................................................................................ 77 ASR ............................................................................................................................................................. 78 B<COND> .................................................................................................................................................. 79 BL ............................................................................................................................................................... 80 BKPT .......................................................................................................................................................... 82 EOR ............................................................................................................................................................ 83 FABS ........................................................................................................................................................... 84 FADD .......................................................................................................................................................... 85 FIX .............................................................................................................................................................. 86 FLOAT ........................................................................................................................................................ 87 FMADD ...................................................................................................................................................... 88 FMUL ......................................................................................................................................................... 88 FMSUB ....................................................................................................................................................... 90 FSUB .......................................................................................................................................................... 91 GID ............................................................................................................................................................. 92 GIE .............................................................................................................................................................