BluespecTM SystemVerilog Reference Guide Revision: 16 June 2010 Copyright c 2000 { 2010 Bluespec, Inc. All rights reserved 1 Reference Guide Bluespec SystemVerilog Trademarks and copyrights Verilog is a trademark of IEEE (the Institute of Electrical and Electronics Engineers). The Verilog standard is copyrighted, owned and maintained by IEEE. VHDL is a trademark of IEEE (the Institute of Electrical and Electronics Engineers). The VHDL standard is copyrighted, owned and maintained by IEEE. SystemVerilog is a trademark of Accellera, Inc. The SystemVerilog standard is owned and maintained by Accellera. Bluespec is a trademark of Bluespec, Inc. AzureIP is a trademark of Bluespec, Inc. 2 Bluespec SystemVerilog Reference Guide Contents Table of Contents 3 1 Introduction 13 1.1 Meta notation........................................ 13 2 Lexical elements 13 2.1 Whitespace and comments................................. 14 2.2 Identifiers and keywords.................................. 14 2.3 Integer literals....................................... 14 2.3.1 Type conversion of integer literals........................ 15 2.4 Real literals......................................... 15 2.4.1 Type conversion of real literals.......................... 16 2.5 String literals........................................ 16 2.6 Don't-care values...................................... 17 2.7 Compiler directives..................................... 17 2.7.1 File inclusion: `include and `line......................... 17 2.7.2 Macro definition and substitution: `define and related directives....... 18 2.7.3 Conditional compilation: `ifdef and related directives.............. 19 3 Packages and the outermost structure of a BSV design 20 3.1 Scopes, name clashes and qualified identifiers...................... 21 3.2 The Standard Prelude package.............................. 22 3.3 AzureIPTM Foundation Libraries............................. 22 4 Types 22 4.1 Polymorphism........................................ 24 4.2 Provisos (brief intro).................................... 24 4.2.1 The pseudo-function valueof (or valueOf).................... 26 4.3 A brief introduction to deriving clauses......................... 26 5 Modules and interfaces, and their instances 27 5.1 Explicit state via module instantiation, not variables.................. 27 5.2 Interface declaration.................................... 28 5.2.1 Subinterfaces.................................... 30 5.3 Module definition...................................... 31 5.4 Module and interface instantiation............................ 33 5.4.1 Short form instantiation.............................. 33 3 Reference Guide Bluespec SystemVerilog 5.4.2 Long form instantiation.............................. 34 5.5 Interface definition (definition of methods)........................ 35 5.5.1 Shorthands for Action and ActionValue method definitions.......... 36 5.5.2 Definition of subinterfaces............................. 37 5.5.3 Definition of methods and subinterfaces by assignment............. 38 5.6 Rules in module definitions................................ 38 5.7 Examples.......................................... 39 5.8 Synthesizing Modules................................... 41 5.8.1 Type Polymorphism................................ 42 5.8.2 Module Interfaces and Arguments........................ 43 6 Static and dynamic semantics 44 6.1 Static semantics...................................... 44 6.1.1 Type checking................................... 44 6.1.2 Proviso checking and bit-width constraints................... 45 6.1.3 Static elaboration................................. 45 6.2 Dynamic semantics..................................... 45 6.2.1 Reference semantics................................ 46 6.2.2 Mapping into efficient parallel clocked synchronous hardware......... 46 6.2.3 How rules are chosen to fire............................ 48 6.2.4 Mapping specific hardware models........................ 49 7 User-defined types (type definitions) 49 7.1 Type synonyms....................................... 50 7.2 Enumerations........................................ 51 7.3 Structs and tagged unions................................. 52 8 Variable declarations and statements 55 8.1 Variable and array declaration and initialization.................... 55 8.2 Variable assignment.................................... 56 8.3 Implicit declaration and initialization........................... 57 8.4 Register reads and writes................................. 58 8.4.1 Registers and square-bracket notation...................... 59 8.4.2 Registers and range notation........................... 60 8.4.3 Registers and struct member selection...................... 60 8.5 Begin-end statements.................................... 61 8.6 Conditional statements................................... 61 8.7 Loop statements...................................... 63 4 Bluespec SystemVerilog Reference Guide 8.7.1 While loops..................................... 63 8.7.2 For loops...................................... 63 8.8 Function definitions.................................... 64 8.8.1 Definition of functions by assignment....................... 65 8.8.2 Function types................................... 66 9 Expressions 66 9.1 Don't-care expressions................................... 66 9.2 Conditional expressions.................................. 67 9.3 Unary and binary operators................................ 67 9.4 Bit concatenation and selection.............................. 68 9.5 Begin-end expressions................................... 69 9.6 Actions and action blocks................................. 69 9.7 Actionvalue blocks..................................... 71 9.8 Function calls........................................ 73 9.9 Method calls........................................ 73 9.10 Static type assertions.................................... 74 9.11 Struct and union expressions............................... 74 9.11.1 Struct expressions................................. 75 9.11.2 Struct member selection.............................. 75 9.11.3 Tagged union expressions............................. 75 9.11.4 Tagged union member selection.......................... 76 9.12 Interface expressions.................................... 77 9.12.1 Differences between interfaces and structs.................... 78 9.13 Rule expressions...................................... 78 10 Pattern matching 80 10.1 Case statements with pattern matching......................... 82 10.2 Case expressions with pattern matching......................... 83 10.3 Pattern matching in if statements and other contexts.................. 84 10.4 Pattern matching assignment statements......................... 85 11 Finite state machines 86 5 Reference Guide Bluespec SystemVerilog 12 Important primitives 86 12.1 The types bit and Bit ................................... 86 12.1.1 Bit-width compatibility.............................. 87 12.2 UInt, Int, int and Integer................................. 87 12.3 String............................................ 87 12.4 Tuples............................................ 87 12.5 Registers........................................... 88 12.6 FIFOs............................................ 89 12.7 FIFOFs........................................... 89 12.8 System tasks and functions................................ 90 12.8.1 Displaying information............................... 90 12.8.2 $format....................................... 91 12.8.3 File data type.................................... 92 12.8.4 Opening and closing file operations....................... 92 12.8.5 Writing to a file.................................. 93 12.8.6 Formatting output to a string........................... 94 12.8.7 Reading from a file................................. 94 12.8.8 Flushing output.................................. 95 12.8.9 Stopping simulation................................ 95 12.8.10 VCD dumping................................... 95 12.8.11 Time functions................................... 95 12.8.12 Real functions................................... 96 12.8.13 Testing command line input............................ 96 13 Guiding the compiler with attributes 96 13.1 Verilog module generation attributes........................... 97 13.1.1 synthesize ..................................... 97 13.1.2 noinline ...................................... 97 13.2 Interface attributes..................................... 97 13.2.1 Renaming attributes................................ 98 13.2.2 Port protocol attributes.............................. 99 13.2.3 Interface attributes example............................ 100 13.3 Scheduling attributes.................................... 101 13.3.1 fire_when_enabled ................................ 101 13.3.2 no_implicit_conditions ............................ 102 13.3.3 descending_urgency ............................... 103 13.3.4 execution_order ................................. 105 6 Bluespec SystemVerilog Reference Guide 13.3.5 mutually_exclusive .............................. 106 13.3.6 conflict_free .................................. 106 13.3.7 preempts ...................................... 107 13.4 Evaluation behavior attributes.............................. 107 13.4.1 split and nosplit ................................ 107 13.5 Input clock and reset attributes.............................. 108 13.5.1 Clock and reset prefix naming attributes..................... 109 13.5.2 Gate synthesis attributes............................