PHYS 162 - Chapter 8 Field Effect Transistor CHAPTER 8 FIELD EFFECT TRANSISTOR (FETs) INTRODUCTION - FETs are voltage controlled devices as opposed to BJT which are current controlled. - There are two types of FETs. o Junction FET (JFET) o Metal Oxide Semiconductor FET (MOSFET) - The basic difference between the two is in terms of their construction. - Both have the advantage of high input resistance and low output resistance as compared to BJT. - Both have an advantage of high power output. 8-1 THE JFET - JFET operate with a reverse biased pn junction to control the current in a channel. - Depending upon the construction, JFETs fall in either of two categories, o n-channel o p-channel - The basic representation of the both is given in Figure 1. - Wires are connected to each end of the n-channel (Figure 1a). - Upper end is the Drain while the lower end is the Source. - Two p-types regions are diffused in the n-channel to form a channel. - Both p-regions are connected to the Gate. Figure 1 Basic structure of JFET 8.1.1 Basic Operation - The basic operation of the JFET is illustrated in Figure 2 which shows a biased n-channel JFET. - VDD is the drain-to-source voltage and provides the drain current ID. - VGG sets the reverse bias between the gate and the source. - JFET is always operated with the gate-source pn junction reverse biased. - The reverse bias produces a depletion region along the pn junction and increases the resistance of the channel which controls the current. Prepared By: Syed Muhammad Asad – Semester 102 Page 1 PHYS 162 - Chapter 8 Field Effect Transistor - Therefore, VGS, the gate-source voltage can be changed to control the amount of drain current ID flowing in the channel. Figure 2 Biased n-channel JFET Figure 3 Effect of VGS on channel width, resistance and drain current 8.1.2 JFET Symbols - The schematic symbols for n-channel and p-channel JFETs are shown in Figure 4. - The “in” arrow on the gate indicates an n-channel JFET while the “out” arrow indicates p-channel. Figure 4 JFET schematic symbols 8.2 JFET CHARACTERISTICS AND PARAMETERS - JFET is a voltage-controlled, constant-current device. - The controlling voltage for JFET is VGS. - Following is an explanation to understand the characteristics and parameters of JFET (Figure 5a): o Consider the case when gate-to-source voltage 푉퐺푆 = 0푉. o As VDD and thus VDS is increased, ID will increase. This is highlighted in the graph of Figure 5b between points A and B. o This region is called the Ohmic Region and in this region channel resistance is constant. o At point B, the curve of Figure 5b levels and enters the active region. o In this region, ID is constant. o As voltage VDS is increased, the drain current ID remains constant between points B and C. Prepared By: Syed Muhammad Asad – Semester 102 Page 2 PHYS 162 - Chapter 8 Field Effect Transistor Figure 5 Drain characteristic curve of a JFET for VGS=0V 8.2.1 Pinch Off - At 푉퐺푆 = 0푉, the value of VDS where ID becomes constant (Point B on Figure 5b) is called Pinch-Off voltage, Vp. - A given JFET has fixed value of Vp given in datasheets. - At 푉퐺푆 = 0푉, the value of the constant drain current is called IDSS (Drain to Source current gate Shorted). - IDSS is given in datasheets. - IDSS is the maximum current a JFET can produce. 8.2.2 Breakdown - Breakdown occurs at point C when ID increases very rapidly. - Breakdown can damage the transistor. - JFETs should be operated below breakdown in the active region (between point B and C). 8.2.3 VGS controls ID - Connect a bias voltage VGG from gate to source as shown in Figure 6a. - As VGS becomes more negative (푉퐺푆 < 0푉), the resistance of the n-channel increases with the increase in the depletion region. - As we keep on decreasing VGS, a family of drain characteristic curves is produced as shown in Figure 6b. - Drain current ID decreases with more negative VGS. - This behavior illustrates that the drain current is controlled by VGS. 8.2.4 Cutoff Voltage - The value of VGS that makes ID approximately zero is the cutoff voltage VGS(off). - A JFET must be operated between 푉퐺푆 = 0푉 and VGS(off). 8.2.5 Comparison of Pinch-Off Voltage and Cutoff Voltage - VGS(off) and Vp are always equal in magnitude but opposite in sign. - So 푉퐺푆 표푓푓 = −푉푝. - Anyone one of the two parameters is mentioned in the datasheet but not both. Prepared By: Syed Muhammad Asad – Semester 102 Page 3 PHYS 162 - Chapter 8 Field Effect Transistor NOTE: REFER EXAMPLE 8-1 PAGE 375 Figure 6 VGS controls ID 8.2.6 JFET Universal Transfer Characteristic - We now know that VGS controls ID. - Therefore the relationship between VGS and ID is very important. - Figure 7 shows a general characteristic curve that graphically shows how VGS and ID are related. - This graph is known as a transconductance curve. Figure 7 JFET universal transfer characteristic curve - Following points need to be noticed about the graph: o 퐼퐷 = 0퐴 when 푉퐺푆 = 푉퐺푆 표푓푓 퐼퐷푆푆 o 퐼 = when 푉 = 0.5푉 퐷 4 퐺푆 퐺푆 표푓푓 퐼퐷푆푆 o 퐼 = when 푉 = 0.3푉 퐷 2 퐺푆 퐺푆 표푓푓 o 퐼퐷 = 퐼퐷푆푆 when 푉퐺푆 = 0푉 - The mathematical relation between the drain current ID and VGS can be given approximately as Prepared By: Syed Muhammad Asad – Semester 102 Page 4 PHYS 162 - Chapter 8 Field Effect Transistor 2 푉퐺푆 퐼퐷 ≈ 퐼퐷푆푆 1 − 푉퐺푆 표푓푓 - The above equation can determine ID for any given value of VGS if IDSS and VGS(off) are known. - IDSS and VGS(off) are given in the datasheets. NOTE: REFER EXAMPLE 8-3 PAGE 377 8.2.7 JFET Forward Transconductance - Transconductance can be roughly defined as the inverse of resistance. - The forward transconductance of the JFET is given by symbol gm. - It is the change in the drain current (Δ퐼퐷) for a given change in the gate-to-source voltage (Δ푉퐺푆) with constant VDS. - It is expressed as a ratio and has a unit of Siemens (S) or mho. Δ퐼퐷 푔푚 = Δ푉퐺푆 - As the JFET transfer curve is nonlinear, gm varies in value on different location of the curve. Figure 8 gm varies depending on VGS - gm is greater at the top (near 푉퐺푆 = 0푉) of the curve as compared to the bottom (near 푉퐺푆 표푓푓 ) as shown in Figure 8. - The datasheet normally gives values of gm at 푉퐺푆 = 0푉 (gm0). - Given gm0, we can calculate gm at any point on the curve using the following formula: Prepared By: Syed Muhammad Asad – Semester 102 Page 5 PHYS 162 - Chapter 8 Field Effect Transistor 푉퐺푆 푔푚 = 푔푚0 1 − 푉퐺푆 표푓푓 - If gm0 is not available, we can use the following formula to calculate it: 2퐼퐷푆푆 푔푚0 = 푉퐺푆 표푓푓 NOTE: REFER EXAMPLE 8-4 PAGE 379 8.2.8 Input Resistance - The input resistance of JFETs is extremely high as compared to BJTs. - This is due to the reverse bias at the gate-to-source junction which increases the depletion region at the junction and thus increases the resistance. - The input resistance can be determined by the following formula: 푉퐺푆 푅퐼푁 = 퐼퐺푆푆 8.3 JFET Biasing - The main purpose of DC biasing is to select the proper DC gate-to-source voltage VGS to establish a desired value of drain current ID which is the Q-point of the circuit. - There are 3 types of bias circuit used with JFETs. o Self Bias o Voltage Divider Bias o Current Source Bias 8.3.1 Self-Bias - Self-bias is the most common type of bias circuit for JFET. - Figure 9 shows the self-bias circuit for n-channel (Figure 9a) and p-channel (Figure 9b) JFETs. - The gate terminal being grounded through RG results in 푉퐺 = 0푉. Figure 9 Self-bias JFET - This setup achieves the reverse bias condition of the gate required for proper biasing of JFET. NOTE: REFER EXAMPLE 8-6 PAGE 382 Prepared By: Syed Muhammad Asad – Semester 102 Page 6 PHYS 162 - Chapter 8 Field Effect Transistor 8.3.2 Setting the Q-Point of a Self Biased JFET - For setting a Q-point, first either find ID for some VGS or vice versa. - Then calculate the required RS by the following relation: 푉퐺푆 푅푆 = 퐼퐷 - For a desired value of VGS, ID can be determined in two ways. o Graphical using the transfer curve. 2 푉퐺푆 o Using Equation of 퐼퐷 ≈ 퐼퐷푆푆 1 − where IDSS and VGS(off) are given. 푉퐺푆 표푓푓 NOTE: REFER EXAMPLE 8-7 PAGE 383 8.3.2.1 Midpoint Bias - It is good to bias a JFET near the midpoint of the transfer curve. - At the midpoint 퐼퐷푆푆 퐼 = 퐷 2 푉퐺푆 표푓푓 푉 = 퐺푆 3.4 푉퐷퐷 푉 = 퐷 2 - Select a value of RD to get the required VD. - Choose RG large enough (mega ohm range). NOTE: REFER EXAMPLE 8-9 PAGE 384 8.3.3 Graphical Analysis of a Self-Biased JFET - The transfer characteristic curve of a JFET can be used to find the Q-point (ID and VGS) of a self biased circuit. - If the curve is not given then it can be plotted using the equation of ID and using the datasheet values of IDSS and VGS(off). - To determine the Q-point of the circuit, a DC load line must be drawn. - The DC load line is established as follows (illustrated in Figure 10): o At 퐼퐷 = 0퐴 find 푉퐺푆 = −퐼퐷푅푆 = 0푉.