The Power MOSFET Application Handbook Design Engineer’s Guide NXP Semiconductors Manchester, United Kingdom 3 The Power MOSFET Application Handbook Design Engineer’s Guide Copyright © NXP Semiconductors www.nxp.com ISBN: 978-0-9934854-0-4 12NC: 9397 750 17686 All rights reserved. No part of this publication may be reproduced or distributed in any form or by any means without the prior written permission of the author. Printed in the United Kingdom 4 Contributors: Andrew Berry Chris Hill Adam Brown Kelly Law Brian Clifton Wayne Lawson Jamie Dyer Koji Nishihata Phil Ellis Jim Parkin Mark Fang Christos Pateropoulos Keith Heppenstall Phil Rutter 5 6 Understanding power MOSFET data sheet parameters 1 Power MOSFET single-shot and repetitive avalanche ruggedness rating 2 Using RC Thermal models 3 LFPAK MOSFET thermal design – part 1 4 LFPAK MOSFET thermal design – part 2 5 Using power MOSFETs in parallel 6 Designing RC snubbers 7 Failure signature of electrical overstress on power MOSFETs 8 Power MOSFET frequently asked questions 9 Abbreviations Index Legal Information 7 8 Table of Contents Chapter 1: Understanding power MOSFET data sheet parameters 1.1 Introduction 18 1.2 Data sheet technical sections 18 1.2.1 Product profile 18 1.2.2 Pinning information 21 1.2.3 Ordering information 21 1.2.4 Limiting values 21 1.2.5 Thermal characteristics 30 1.2.6 Electrical characteristics 31 1.2.7 Package outline 42 1.3 Appendices 43 1.3.1 Safe Operating Area (SOA) curves 43 1.4 References 50 Chapter 2: Power MOSFET single-shot and repetitive avalanche ruggedness rating 2.1 Introduction 52 2.2 Single-shot and repetitive avalanche definitions 52 2.3 Understanding power MOSFET single-shot avalanche events 53 2.3.1 Single-shot UIS operation 53 2.3.2 Single-shot avalanche ruggedness rating 56 2.4 Understanding power MOSFET repetitive avalanche events 57 2.4.1 Repetitive UIS operation 58 2.4.2 Temperature components 59 2.5 Repetitive avalanche ruggedness rating 59 2.6 Conclusion 60 2.7 Examples 61 2.7.1 Single-shot avalanche case 61 2.7.2 Repetitive avalanche case 61 2.8 References 62 9 Chapter 3: Using RC Thermal Models 3.1 Introduction 64 3.2 Thermal impedance 64 3.3 Calculating junction temperature rise 65 3.4 Association between Thermal and Electrical parameters 66 3.5 Foster RC thermal models 67 3.6 Thermal simulation examples 70 3.6.1 Example 1 70 3.6.2 Example 2 73 3.6.3 Example 3 77 3.7 Discussions 79 3.8 Summary 80 3.9 References 80 Chapter 4: LFPAK MOSFET thermal design - part 1 4.1 Introduction 82 4.1.1 The need for thermal analysis 82 4.1.2 MOSFET Rth parameters and their limitations 83 4.1.3 Aim of this chapter 84 4.2 General approach to thermal analysis 85 4.2.1 The use of thermal simulation software 85 4.2.2 Simulation set-up 86 4.2.3 PCB layout and stack-up 86 4.3 A single LFPAK device 88 4.3.1 Analysis 1: A single-layer PCB 88 4.3.2 Analysis 2: 2-layer PCB 94 4.3.3 Analysis 3: A 4-layer PCB part 1 96 4.3.4 Analysis 3: A 4-layer PCB part 2 98 4.3.5 Analysis 4: A 4-layer PCB with thermal vias part 1 99 4.3.6 Analysis 4: A 4-layer PCB with thermal vias part 2 102 4.3.7 Summary: factors affecting the thermal performance of a single device 103 4.4 Two LFPAK devices 103 4.4.1 Analysis 5: A single-layer PCB 105 10 4.4.2 Analysis 6: A 2-layer PCB 106 4.4.3 Analysis 7: A generalized 4-layer PCB 107 4.4.4 Analysis 8: A 4-layer PCB with thermal vias part 1 108 4.4.5 Analysis 8: A 4-layer PCB with thermal vias part 2 112 4.4.6 Summary: factors affecting the thermal performance of two devices 113 4.5 Four LFPAK devices 113 4.5.1 Analysis 9: A single-layer PCB 114 4.5.2 Analysis 10: A 2-layer PCB 115 4.5.3 Analysis 11: A generalized 4-layer PCB 116 4.5.4 Analysis 12: A 4-layer PCB with thermal vias part 1 117 4.5.5 Analysis 12: A 4-layer PCB with thermal vias part 2 119 4.5.6 Summary; factors affecting the thermal performance of four devices 121 4.6 Summary 121 Chapter 5: LFPAK MOSFET thermal design - part 2 5.1 Introduction 124 5.2 The module model 125 5.2.1 PCB characteristics 125 5.2.2 Enclosure characteristics 126 5.2.3 Axes naming convention 128 5.2.4 The ambient environment 128 5.2.5 Potential heat paths 128 5.3 The influence of y-gap on Tj 129 5.3.1 Black plastic enclosure; x- and z-gaps = zero 129 5.3.2 Two more enclosure materials 133 5.3.3 Summary: the influence of y-gap on Tj 135 5.4 Adding x- and z-gaps around the PCB 135 5.4.1 The black plastic enclosure 136 5.4.2 The polished aluminium enclosure 137 5.4.3 The anodized aluminium enclosure 138 5.4.4 The three enclosures side-by-side 139 5.4.5 Summary: adding x- and z-gaps around the PCB 141 5.5 Encapsulating the PCB 141 5.5.1 Partial encapsulation 143 11 5.5.2 Full encapsulation 146 5.5.3 Summary: encapsulating the PCB 149 5.6 Direct cooling through the enclosure 149 5.6.1 Bottom-side cooling of the PCB 149 5.6.2 Bottom-side cooling of the PCB, with encapsulation 152 5.6.3 Top-side cooling of the PCB 155 5.6.4 Top-side cooling of the PCB, with encapsulation 158 5.6.5 Summary: direct cooling through the enclosure 160 5.7 Mounting the enclosure on a bulkhead 160 5.7.1 Vertical orientation of the module 161 5.7.2 Adding the bulkhead 162 5.7.3 Results for the PCB mounted centrally in the module 164 5.7.4 Results for the PCB with bottom-side cooling 165 5.7.5 Results for the PCB with top-side cooling 167 5.7.6 Summary: mounting the enclosure on a bulkhead 168 5.8 Summary 168 Chapter 6: Using power MOSFETs in parallel 6.1 Introduction 172 6.2 Static (DC) operation 173 6.2.1 Worked examples for static operation 174 6.3 MOSFET mounting for good thermal performance and power sharing 178 6.4 Power sharing in dynamic operation [pulse and Pulse Width Modulation (PWM) circuits] 181 6.5 Partially enhanced (linear mode) power sharing 183 6.6 Gate drive considerations 184 6.6.1 Should individual gate drivers be used for each MOSFET in the group? 185 6.7 MOSFET packaging considerations for paralleled groups 185 6.7.1 Bare die (KGD) MOSFETs 185 6.7.2 LFPAK MOSFETs 186 6.8 Inductive energy dissipation in paralleled MOSFETs 186 6.8.1 Avalanching - low side MOSFET group driving a high side inductive load 186 12 6.8.2 Active clamping - high side MOSFET group driving a low side inductive load 187 6.9 Summary 188 Chapter 7: Designing RC snubbers 7.1 Introduction 190 7.2 Test circuit 190 7.3 Determining CLK and LLK 192 7.4 Designing the snubber - theory 194 7.5 Designing the snubber - in practice 196 7.6 Summary 197 7.7 Appendix A; determining CLK from Cadd, fRING0 and fRING1 198 Chapter 8: Failure signature of electrical overstress on power MOSFETs 8.1 Introduction 200 8.1.1 ESD - Machine Model 201 8.1.2 ESD - Human body model 203 8.1.3 Unclamped Inductive Switching (UIS) (Avalanche or Ruggedness) 204 8.1.4 Linear mode operation 206 8.1.5 Over-current 208 8.2 Appendices 211 8.2.1 Machine model EOS of BUK9508-55A 211 8.2.2 Machine model EOS of BUK9Y40-55B 212 8.2.3 Machine model EOS of PSMN7R0-30YL 214 8.2.4 Machine model EOS of PSMN011-30YL 215 8.2.5 Human body model EOS of BUK9508-55A 217 8.2.6 Human body model EOS of BUK9Y40-55B 218 8.2.7 Human body model EOS of PSMN011-30YL 219 8.2.8 Unclamped inductive switching EOS of BUK7L06-34ARC 220 8.2.9 Unclamped Inductive switching EOS of BUK9Y40-55B 222 8.2.10 Unclamped inductive switching EOS of PSMN7R0-30YL 223 8.2.11 Linear mode EOS of BUK7L06-34ARC 224 8.2.12 Linear mode EOS of BUK9Y40-55B 226 8.2.13 Linear mode EOS of PSMN7R0-30YL 228 8.2.14 Over-current EOS of BUK7L06-34ARC 230 13 8.2.15 Over-current EOS of PSMN7R0-30YL 232 8.3 Tables 233 8.4 Figures 234 Chapter 9: Power MOSFET frequently asked questions 9.1 Introduction 238 9.2 Gate 238 9.3 Thermal impedance (Zth) curves 239 9.4 MOSFET body diode 244 9.5 Safe operating area and linear mode operation 246 9.6 Avalanche Ruggedness and Unclamped Inductive Switching (UIS) 250 9.7 Capacitive dV/dt issues 258 9.8 Package and mounting 263 9.9 SPICE models 265 9.10 MOSFET silicon technology 266 9.11 Supply and availability 268 9.12 EMC 268 9.13 Leakage, breakdown and MOSFET characteristics 269 9.14 MOSFET reliability 277 14 Introduction Drawing on over 20 years’ of experience, the Power MOSFET Application Handbook brings together a comprehensive set of learning and reference materials relating to the use of power MOSFETs in real world systems.