Specification for I3CSM Improved Inter Integrated Circuit Version 1.0 23 December 2016 MIPI Board Adopted 31 December 2016 Public Release Edition Further technical changes to this document are expected as work continues in the Sensor Working Group. Copyright © 2016–2017 MIPI Alliance, Inc. Specification for I3C Version 1.0 23-Dec-2016 NOTICE OF DISCLAIMER The material contained herein is provided on an “AS IS” basis. To the maximum extent permitted by applicable law, this material is provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI Alliance Inc. (“MIPI”) hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of negligence. 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Public Release Edition Version 1.0 Specification for I3C 23-Dec-2016 Contents Contents ............................................................................................................................ iii Figures .............................................................................................................................. vii Tables ...................................................................................................................................x Release History ............................................................................................................... xiii 1 Introduction ..............................................................................................................1 1.1 Scope ............................................................................................................................... 2 1.2 I3C Purpose .................................................................................................................... 2 1.3 I3C Key Features ........................................................................................................... 3 2 Terminology ..............................................................................................................5 2.1 Use of Special Terms ...................................................................................................... 5 2.2 Definitions ....................................................................................................................... 5 2.3 Abbreviations ................................................................................................................. 8 2.4 Acronyms ........................................................................................................................ 8 3 References ...............................................................................................................10 3.1 Normative References .................................................................................................. 10 3.2 Informative References ............................................................................................... 10 4 Technical Overview (Informative) ........................................................................ 11 4.1 I3C Fundamental Principles ....................................................................................... 12 4.2 I3C Master and Slave Devices .................................................................................... 15 4.2.1 I3C Master Device .................................................................................................... 16 4.2.1.1 I3C Master Device Roles ..............................................................................................17 4.2.2 I3C Slave Device ....................................................................................................... 18 4.2.2.1 I3C Slave Device Roles .................................................................................................19 5 I3C Protocol ............................................................................................................20 5.1 Single Data Rate (SDR) Mode .................................................................................... 20 5.1.1 Bus Configuration .................................................................................................... 21 5.1.1.1 I3C Device Characteristics ...........................................................................................21 5.1.1.2 I3C Characteristics Registers ......................................................................................24 5.1.1.2.1 Bus Characteristics Register (BCR)...........................................................................25 5.1.1.2.2 Device Characteristics Register (DCR) .....................................................................26 5.1.1.2.3 Legacy Virtual Register (LVR) ..................................................................................26 5.1.2 Bus Communication ................................................................................................. 27 5.1.2.1 Role of I3C Slave ...........................................................................................................28 5.1.2.2 I3C Address Header ......................................................................................................29 5.1.2.2.1 I3C Address Arbitration .............................................................................................30 5.1.2.2.2 I3C Address Arbitration Optimization .......................................................................30 5.1.2.2.3 Consequence of Master Starting a Frame with an I3C Slave Address .......................31 5.1.2.2.4 Address Header Following a Repeated START is Push-Pull .....................................32 5.1.2.2.5 I3C Slave Address Restrictions ..................................................................................32 5.1.2.3 I3C SDR Data Words ....................................................................................................34 5.1.2.3.1 Transition from Address ACK to SDR Master Write Data ........................................34 5.1.2.3.2 Ninth Bit of SDR Master Written Data as Parity .......................................................35 5.1.2.3.3 Ninth Bit of SDR Slave Returned (Read) Data as End-of-Data ................................35 Copyright © 2016–2017 MIPI Alliance, Inc. iii Public Release Edition Specification for I3C Version 1.0 23-Dec-2016 5.1.2.4 Use of Clock Speed to Prevent Legacy I2C Devices From Seeing I3C Traffic .........36 5.1.2.4.1 Use of Duty Cycle to Achieve Lower Effective Speed in a Mixed Fast Bus .............36 5.1.2.5 Master Clock Stalling ...................................................................................................37 5.1.2.5.1 I3C/I2C Transfer, ACK/NACK Phase ........................................................................38 5.1.2.5.2 Write Data Transfer,