Designing with FPGAs and CPLDs Bob Zeidman CMP Books Lawrence, Kansas 66046 CMP Books CMP Media LLC 1601 West 23rd Street, Suite 200 Lawrence, Kansas 66046 USA www.cmpbooks.com Designations used by companies to distinguish their products are often claimed as trademarks. In all instances where CMP Books is aware of a trademark claim, the product name appears in initial capital letters, in all capital letters, or in accordance with the vendor’s capitalization preference. Readers should contact the appropriate companies for more complete information on trademarks and trademark registrations. All trademarks and registered trademarks in this book are the prop- erty of their respective holders. Copyright © 2002 by CMP Books, except where noted otherwise. Published by CMP Books, CMP Media LLC. All rights reserved. Printed in the United States of America. No part of this publica- tion may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system, without the prior written permission of the publisher. The programs in this book are presented for instructional value. The programs have been carefully tested, but are not guaranteed for any particular purpose. The publisher does not offer any war- ranties and does not guarantee the accuracy, adequacy, or completeness of any information herein and is not responsible for any errors or omissions. The publisher assumes no liability for damages resulting from the use of the information in this book or for any infringement of the intellectual property rights of third parties that would result from the use of this information. Acquisition Editor: Robert Ward Layout design & production: Justin Fulmer and Michelle O’Neal Managing Editor: Michelle O’Neal Cover art design: Damien Castaneda Distributed in the U.S. by: Distributed in Canada by: Publishers Group West Jaguar Book Group 1700 Fourth Street 100 Armstrong Avenue Berkeley, California 94710 Georgetown, Ontario M6K 3E7 Canada 1-800-788-3123 905-877-4483 www.pgw.com ISBN: 1-57820-112-8 This book is dedicated to two smart, dedicated, inspiring teachers who departed this world much too soon, but left a legacy of enthusiastic engineers, mathematicians, and sci- entists. Mrs. Anita Field was my ninth grade teacher at George Washington High School in Phila- delphia. She demonstrated to classes of restless, awkward, prepubescent boys and girls that math could be fun and exciting. She showed by her example that those who studied math could be cultured, well-rounded, and even pretty. Mr. Gordon Stremlau was a human calculating machine with a dry sense of humor that we only understood when we were seniors at GWHS. What we first thought were snide remarks and nasty smirks, as freshman, we later came to realize were clever comments and inside jokes. It was only after some level of maturity that we could appreciate the sub- tlety of his wit. Both of these people were mentors, and friends, and I wish that I had the opportunity to thank them personally. And though I’m saddened by the fact that there are few others like them, as dedicated and excited, teaching our children, there is some comfort in knowing that I and my friends have benefited from knowing them. This Page Intentionally Left Blank Table of Contents Foreword . ix Preface . xi Book Organization . xi Intended Audience . xiv Content . .xv Support and Feedback . xv Acknowledgments . xvi Chapter 1 Prehistory: Programmable Logic to ASICs . 1 Objectives . .1 1.1 Programmable Read Only Memories (PROMs). .2 1.2 Programmable Logic Arrays (PLAs) . .5 1.3 Programmable Array Logic (PALs) . .6 1.4 The Masked Gate Array ASIC. .13 1.5 CPLDs and FPGAs . .15 1.6 Summary . .15 Exercises . .16 Chapter 2 Complex Programmable Logic Devices (CPLDs) 17 Objectives . .17 2.1 CPLD Architectures. .18 2.2 Function Blocks. .18 2.3 I/O Blocks . .20 v vi Table of Contents 2.4 Clock Drivers. 20 2.5 Interconnect. 21 2.6 CPLD Technology and Programmable Elements . 23 2.7 Embedded Devices . 25 2.8 Summary: CPLD Selection Criteria . 27 Exercises . 30 Chapter 3 Field Programmable Gate Arrays (FPGAs) . .33 Objectives . 33 3.1 FPGA Architectures . 34 3.2 Configurable Logic Blocks . 34 3.3 Configurable I/O Blocks . 37 3.4 Embedded Devices . 40 3.5 Programmable Interconnect . 40 3.6 Clock Circuitry . 42 3.7 SRAM vs. Antifuse Programming . 43 3.8 Emulating and Prototyping ASICs . 45 3.9 Summary . 48 Exercises . 51 Chapter 4 Universal Design Methodology for Programmable Devices . .55 Objectives . 55 4.1 What is UDM and UDM-PD? . 56 4.2 Writing a Specification. 57 4.3 Specification Review . 63 4.4 Choosing Device and Tools . 63 4.5 Design . 63 4.6 Verification . 65 4.7 Final Review . 68 4.8 System Integration and Test. 68 4.9 Ship Product! . 68 4.10 Summary . 69 Exercises . 70 Chapter 5 Design Techniques, Rules, and Guidelines . .73 Objectives . 74 5.1 Hardware Description Languages . 74 Table of Contents vii 5.2 Top-Down Design . .88 5.3 Synchronous Design . .92 5.4 Floating Nodes . .108 5.5 Bus Contention . .109 5.6 One-Hot State Encoding . .110 5.7 Design For Test (DFT) . .111 5.8 Testing Redundant Logic. .113 5.9 Initializing State Machines. .115 5.10 Observable Nodes . .116 5.11 Scan Techniques . .116 5.12 Built-In Self-Test (BIST). .118 5.13 Signature Analysis . .120 5.14 Summary . ..