Memory Definitions CMPT-150 Introduction to Computer Design • Memory : A collection of storage cells together with the necessary circuits to transfer information to and from them. SFU, Harbour Centre, Spring 2007 • Memory Data : a bit or a collection of bits to be stored into or Lecture 16: Mar. 6, 2007 accessed from memory cells. • Typical data elements: • Memory Basics – Bit : a single bi nary digi t. – Random Access Memory (RAM) – Byte : a collection of 8 bits. • Computer Design Basics – Word : a collection of bits that is the a typical unit of – General Purpose Computer access for the memory. Usually a power of two multiple of bytes (e.g., 1 byte, 2 bytes, 4 bytes, 8 bytes, etc.) – Instruction Set Architecture – Datapath Memory Definitions (cont’) Example • Memory size is measured by the number of bytes or words. • 1K x 16 RAM: 1K words, 10 – Kilo (Kb): 1024 bytes = 2 bytes each of size 16 bits. – Megabyte (Mb): 1024 Kilobyte = 2 20 bytes • There are 1024 addresses – Gigabyte (Gb): 1024 Megabyte = 2 30 bytes (0-1023 decimal, or – Terabyte (Tb): 1024 Gigabyte = 2 40 bytes 0000000000-1111111111 • Memory Organization: Usually organized as an indexed array binary). of words. Index = Address . • Reading the word at • Memory Operations: operations on memory data supported by address 1021 = 1111111101 the memory unit. Usually, Read and Write . we get 1001110100010101 • Random Access Memory (RAM) : Time to access memory cells is independent of their address. – Not random access: Memory Block Diagram Memory Block Diagram (cont’) n • k address lines are decoded k • Example: to address 2 words of k memory. • Each word has n bits. n • When Read=1 the n output data contain the data at the address specified by the • CS enables the memory. k address lines. • R/W determines whether memory is read or written. • When Write=1 the content of the memory at the address • 64K = 2 6·210 = 2 16 16 address bits specified by the k address lines is changed to the data • The size of a word stored in memory is 8 bits 8 output bits. specified by n input data lines. Implementation Constructing Large RAMs from Small RAMs • Small memories can be constructed from registers and • n 8x1 RAMs can be used to construct 8xn RAM combinatorial components. For large memories, other 8x3 RAM technologies are used. 3 Addr Data • Example: 8 x 1 RAM – 8 words of size 1. 8x1 RAM 8x1 RAM 8x1 RAM 3 3 – A 3 8 decoder is used 3 Addr Addr Addr Data Data Data to enable writing to Out Out Out CS exactly one cell. CS CS R/W R/W R/W – An 8 1 Mux is CS used to select the cell R/W to read. – Alternatively, use a bus. • Actually, no need to duplicate the Decoder. Constructing Large RAMs from Small RAMs (cont’) General Purpose Computer • n 8x1 RAMs can be used to construct 8n x1 RAM • So far we design digital circuits that perform specific tasks. This approach is useful for: 16 1 RAM 3 Addr x – “Simple” tasks resulting in small circuits – Large numbers of such circuits are required 21 Decoder • Sometimes it’s better to design a general purpose circuit 8x1 RAM 8x1 RAM CS EN 3 Addr 3 Addr (computer), which can perform different sets of instructions Data Data Out Out (programs). CS CS R/W R/W • Instructions are: R/W – Given through input devices bus (keyboard, Hard Disk) – Kept in memory – Performed by the Central Processing Unit (CPU) General Purpose Computer (cont’) General Purpose Computer (cont’) • Instructions a typical CPU is capable of performing: • Instruction Set Architecture (ISA) : The set of instructions – Data transfer : values can be transferred between the CPU can perform. This is the lower-level “appearance” of registers in the CPU and external memory. the computer to a (software) programmer. – Arithmetic : values stored in registers can be combined Corresponds to Machine/Assembly Language . using arithmetic operations. – Logic : values in registers can be combined using logic • Computer Architecture: High-level description of the operations. hardware (CPU) that implements the ISA. Usually, divided to – Shifting the content of registers. Datapath and Control Unit . Datapath – Testing : the results of operations can be tested to detect • Datapath: Performs the conditions such as overflow, carry, negative result, zero. Registers file data-processing operations. Control Unit – Input/output : values can be retrieved from external ALU devices or displayed on them. • Control Unit: Determines the – Branching : Changing the sequence of executed instruction sequence of operations. during execution. System Datapath Block Diagram Arithmetic and Logic Unit (ALU) • The main components of the datapath are the Register File and the Arithmetic and Logic Carry out Negative Unit (ALU) . Zero Overflow • ALU: the combinatorial part that performs the arithmetic and logic operations. • The operands of the ALU are (the values in) in at most two Implements a variety of registers selected by the control. binary (2 operands) and • Control signals determine the operation performed by the unary (1 operand) arithmetic and operations. ALU. • Data bus connects the main memory and the register file. Datapath: Example Instruction Set Architecture • A possible instruction*: • ISA is the language “understood” by the CPU. ADD R1,R2,R3; • Every CPU has its own ISA. (sum the values in R2 and R3 • (Software) programmers can use the ISA to write programs to and write the result to R1 ) be executed by the CPU. • To implement it: – A select = R2 • Example: – B select = R3 – G select = A+B – MF select = ALU – MD select = F – Destination select = R1 • Opcode is a binary codeword for the instruction. – Load enable = 1 • An instruction usually has several parameters. • Example: 0000101 001 011 010 * Not necessarily a real command. Subtract R1 R3 R2 R1 R3 – R2 The Fetch-Execute Cycle • The steps perform by the control unit when executing a program: 1. Fetch the next instruction to be executed from memory. 2. Decode the instruction: a combinatorial part that determines the control signals. 3. Execute the instruction and (possibly) store the result. 4. Go to step 1..