The Shock and Awe VHDL Tutorial ©Copyright: 2007 by Bryan Mealy (01-01-2007) 1 The Shock and Awe VHDL Tutorial 9/13/05 Table of Contents TABLE OF CONTENTS.............................................................................................................. 2 LIST OF FIGURES....................................................................................................................... 5 LIST OF TABLES......................................................................................................................... 7 LIST OF EXAMPLES................................................................................................................... 8 1. INTENT AND PURPOSE..................................................................................................... 9 2. INTRODUCTION............................................................................................................- 10 - 2.1 THE GOLDEN RULES OF VHDL..................................................................................... - 11 - 3. VHDL INVARIANTS......................................................................................................- 12 - 3.1 CASE SENSITIVITY .......................................................................................................... - 12 - 3.2 WHITE SPACE.................................................................................................................. - 12 - 3.3 COMMENTS ..................................................................................................................... - 12 - 3.4 PARENTHESIS .................................................................................................................. - 13 - 3.5 VHDL STATEMENTS....................................................................................................... - 13 - 3.6 IF, CASE,AND LOOP STATEMENTS .................................................................................. - 13 - 3.7 IDENTIFIERS .................................................................................................................... - 14 - 3.8 RESERVED WORDS ......................................................................................................... - 14 - 3.9 VHDL CODING STYLE ................................................................................................... - 15 - 4. BASIC VHDL DESIGN UNITS ......................................................................................... 16 4.1 THE ENTITY ........................................................................................................................ 16 4.2 THE ARCHITECTURE .......................................................................................................... 19 4.3 IMPORTANT POINTS............................................................................................................ 20 4.4 EXERCISES: BASIC VHDL DESIGN UNITS......................................................................... 21 5. THE VHDL PROGRAMMING PARADIGM.................................................................. 23 5.1 CONCURRENT STATEMENTS .............................................................................................. 23 5.2 THE SIGNAL ASSIGNMENT OPERATOR “<=”.................................................................... 25 5.3 CONCURRENT SIGNAL ASSIGNMENT STATEMENTS ......................................................... 26 5.4 CONDITIONAL SIGNAL ASSIGNMENT ................................................................................ 29 5.5 SELECTED SIGNAL ASSIGNMENT....................................................................................... 32 2 The Shock and Awe VHDL Tutorial 9/13/05 5.6 THE PROCESS STATEMENT ................................................................................................ 36 5.7 IMPORTANT POINTS............................................................................................................ 36 5.8 EXERCISES: CONCURRENT, CONDITIONAL, AND SELECTIVE SIGNAL ASSIGNMENT..... 37 6. STANDARD MODELS IN VHDL ARCHITECTURES ................................................. 41 6.1 VHDL DATAFLOW STYLE ARCHITECTURE...................................................................... 41 6.2 VHDL BEHAVIOR STYLE ARCHITECTURE ....................................................................... 41 6.3 THE PROCESS STATEMENT ................................................................................................ 42 6.4 SEQUENTIAL STATEMENTS ................................................................................................ 43 6.4.1 SIGNAL ASSIGNMENT STATEMENTS ................................................................................. 44 6.4.2 IF STATEMENTS................................................................................................................. 44 6.4.3 CASE STATEMENTS ........................................................................................................... 47 6.5 CAVEATS REGARDING SEQUENTIAL STATEMENTS.......................................................... 50 6.6 IMPORTANT POINTS............................................................................................................ 51 6.7 EXERCISES: INTRODUCTION TO BEHAVIORAL MODELING ............................................. 52 7. VHDL OPERATORS .......................................................................................................... 54 7.1 LOGICAL OPERATORS ........................................................................................................ 54 7.2 RELATIONAL OPERATORS ................................................................................................. 54 7.3 SHIFT OPERATORS.............................................................................................................. 55 7.4 ALL THE OTHER OPERATORS ............................................................................................ 55 7.5 THE CONCATENATION OPERATOR.................................................................................... 56 7.6 THE MODULUS AND REMAINDER OPERATORS................................................................. 56 8. REVIEW (OF ALMOST EVERYTHING UP TO NOW) ............................................... 58 9. USING VHDL FOR SEQUENTIAL CIRCUITS ............................................................. 60 9.1 SIMPLE STORAGE ELEMENTS USING VHDL .................................................................... 60 9.2 INDUCING MEMORY: DATAFLOW VS. BEHAVIOR MODELING......................................... 64 9.3 IMPORTANT POINTS............................................................................................................ 65 9.4 EXERCISES: BASIC MEMORY ELEMENTS.......................................................................... 66 10. FINITE STATE MACHINE DESIGN USING VHDL................................................... 68 10.1 VHDL BEHAVIORAL REPRESENTATION OF FSMS ........................................................ 69 10.2 ONE-HOT ENCODING FOR FSMS..................................................................................... 77 10.3 IMPORTANT POINTS.......................................................................................................... 80 10.4 EXERCISES: BEHAVIORAL MODELING OF FINITE STATE MACHINES........................... 82 11. STRUCTURAL MODELING USING VHDL ................................................................ 88 11.1 VHDL AND PROGRAMMING LANGUAGES: EXPLOITING THE SIMILARITIES ............... 88 11.2 IMPORTANT POINTS.......................................................................................................... 94 3 The Shock and Awe VHDL Tutorial 9/13/05 11.3 EXERCISES: STRUCTURAL MODELING............................................................................ 95 12. REGISTERS AND REGISTER TRANSFER LEVEL................................................... 97 12.1 IMPORTANT POINTS........................................................................................................ 102 12.2 EXERCISES: REGISTER TRANSFER LEVEL CIRCUITS................................................... 103 13. DATA OBJECTS ............................................................................................................. 105 13.1 TYPES OF DATA OBJECTS .............................................................................................. 105 13.2 DATA OBJECT DECLARATIONS...................................................................................... 105 13.3 VARIABLES AND THE ASSIGNMENT OPERATOR “:=”................................................... 106 13.4 SIGNALS VS. VARIABLES................................................................................................. 106 13.5 DATA TYPES .................................................................................................................... 107 13.6 COMMONLY USED TYPES............................................................................................... 107 13.7 INTEGER TYPES .............................................................................................................. 107 13.8 THE STD_LOGIC TYPE .................................................................................................... 108 14. LOOPING CONSTRUCTS............................................................................................. 111 14.1 FOR AND WHILE LOOPS .................................................................................................