Computer Architecture What is Computer Architecture Review of Basic From Wikipedia, the free encyclopedia In computer science and engineering, computer architecture refers to specification of the relationship between different hardware components of a computer system. It may also Computer refer to the practical art of defining the structure and relationship of the subcomponents of a computer. Architecture This article needs attention from an expert in computer science. החומר בפרק הזה חוזר בקצרה על תוכן הקורס ארכיטקטורה לתואר ראשון במכללת הדסה. במידה שהחומר הזה לא מוכר מומלץ לפנות לאתר https://cs.hac.ac.il/staff/martin/Architecture Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 1 Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 2 Computer Architecture Theory —Goals — Specification What is Computer Architecture Theory von Neumann Architecture Definition 2.0 Computation components CPU: ALU + memory + control input memory output In computer science and engineering, computer architecture Instructions refers to the study of performance in computer systems. Performance = run-time speed Arithmetic It also refers to the practical science of applying Run-time of what? Logic Unit performance theory to specifying the structure and Compared to what? (ALU) relationship of the subcomponents of a computer. Requirements controller Word processing Number crunching data/instruction path From an expert in computer science. Gaming control path Web server Real time Specification Requirements + performance theory component implementation Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 3 Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 4 Requirements — Relative to Application Fundamental Architectural Abstractions Fastest CPU — Xeon E-2278G Digital computer High-end version of Intel x86-64 processor family Machine that can be programmed to process symbols IA-32 instruction set on enhanced P6 micro-architecture Data Netburst Ivy Bridge Haswell Broadwell Skylake Comet Lake Symbol with no intrinsic meaning to machine Pentium II Pentium III Pentium 4 Multicore User imposes meaning — Integer, float, string, ... Operation Smartphones — ARM CPU Symbol describing processing of data symbols Low power Machine interprets meaning — transfer, ALU, control, OS, ... Higher performance / Watt than x86 Instruction Fastest supercomputer — Fujitsu Fugaku Symbol describing operation on data 158,976 nodes x 48 cores/node = 7,630,848 cores Machine language = collection of legal instructions Node = ARM v8.2-A CPU Addressing Mode Total RAM = 4.85 PiB = 1024 x 1024 GB Specifies data location as operand Source operand — data input to operation Destination operand — data output from operation Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 5 Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 6 Stages in Computer Design Typical Operations Instruction Set Architecture (ISA) Data transfer 1. Define universe of problems to be solved Load (r m), store (m r), move (r/m r/m), convert data types 2. Study candidate operations at level of system programmer Arithmetic/Logical (ALU) • Atomic — operations complete sequentially Integer arithmetic (+ – compare shift) and logical (AND, OR, NOR, XOR) • General operation = combination of atomic operations Decimal 3. Specify instruction set for machine language Integer arithmetic on decimal numbers • Choose minimum set of orthogonal operations Floating point (FPU) • Not too many ways to solve same problem Floating point arithmetic (+ – sqrt trig exp …) String Implementation String move, string compare, string search 1. Design machine as implementation of ISA Control 2. Evaluate theoretical performance Conditional and unconditional branch, call/return, trap 3. Identify performance problem areas Operating System 4. Improve processor efficiency System calls, virtual memory management instructions Graphics Pixel operations, compression/decompression operations Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 7 Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 8 Memory Hierarchy CPU and Memory Hierarchy CPU controller accesses L1 cache Memory locations Memory location Memory location in or Memory location outside CPU and RAM outside CPU near CPU inside CPU if (L1 cache hit) {access performed in 1 clock cycle} else { Stores data and Stores "all" data and Fast access to important Fast access to small instructions of "all" instructions of data and instructions amount of L1 cache miss — L1 cache accesses cache controller programs running programs from RAM information cache controller initiates access to L2 and main memory if (address in L2 cache) {controller copies contents to L1 from L2} Organized by OS Organized by Copy of RAM section Organized by CPU addresses else {controller copies location to L1 from main memory} } CPU Long Term Main Memory I/O Cache Register ALU L1 instructions cache Main Storage (RAM) L2 Registers controller Memory L1 data Disk Next Few All Files Running Programs Current Instructions request and Data and Data Data access in 1 CC and Data update access latency >> 1 clock cycle Cache miss penalty Address not in L1 delay in memory access Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 9 Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 10 Specifying Operands Addressing Modes Immediate Constant = IMM = numerical value coded into instruction Mode Syntax Memory Access Use Register R3 Regs[R3] Register data Register operands Immediate #3 3 Constant Direct = a CPU storage location R3 (1001) Mem[1001] Static data register name (absolute) REGS[register name] = data stored in register 11223340 Register (R1) Mem[Regs[R1]] Pointer REGS[R3] = data stored in register R3 = 11223340 deferred Displacement 100(R1) Mem[100+Regs[R1]] Local variable Indexed (R1 + R2) Mem[Regs[R1]+Regs[R2]] Array addressing Memory operands 11223344 Memory address = a memory storage location @(R3) Mem[Mem[Regs[R3]]] Pointer to pointer 45 indirect MEM[address] = data stored in memory Auto Mem[Regs[R2]] (R2)+ Stack access Increment MEM[11223344] = data stored at address 11223344 = 45 Regs[R2] Regs[R2]+d Auto Regs[R2] Regs[R2]-d -(R2) Stack access Effective Address (EA) — pointer arithmetic Decrement Mem[Regs[R2]] REGS[R3] &(variable) Scaled 100(R2)[R3] Mem[100+Regs[R2]+Regs[R3]*d] Indexing arrays Load instruction to PC-relative (PC) Mem[PC+value] MEM[REGS[R3]+4] = *(&(variable)+4) = *(REGS[R3]+4) data register PC-relative Load instruction to = *(11223340+4) = 45 1001(PC) Mem[PC+Mem[1001]] deferred data register Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 11 Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 12 Commitment to State Complex Instruction Set Computer (CISC) Internal registers Classic Machine Design Temporary registers used in executing machine instructions 300 instruction types Not visible to programs 15 addressing modes 10 data types Complex machine implementations Architectural state CPU registers visible to programs Mainframes (1955 — 2000) Large, expensive, centralized computers for big business and government System state Manufacturers: IBM, Control Data, Burrows, Honeywell All data resources visible to programs Minicomputers (1965 — 1990) Architectural state + system memory Smaller computers for smaller organizations Manufacturers: Digital (PDP/VAX), Data General (Eclipse) Commitment to state CISC microprocessors (1979 — 1996) Update of system state 6800 (1974) and 8086 (1978) designed as tiny CISC on chip Write to architectural state / system memory Apple II (1977) — 6502 (1975) IBM PC (1981) — 8088 (1979) Intel x86 for PC/Mac = last CISC ISA still manufactured. Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 13 Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 14 Why CISC? Physical Implementation of CISC —Generic Machine Semantic Gap Argument ALU Subsystem Computer language should imitate natural language Large vocabulary + high redundancy flexibility + power 1 3 OUT Registers Terrible compilers IN 2 Limited optimization ALU Operation Limited error messaging ALU Result Flag Efficient code written or optimized in assembly language System Bus Expensive memory RAM < $0.01/MB since 2015 Status control RAM ~ $5000/MB wholesale in 1977 Decoder IR PC MAR MDR Word + Implications for machine language Design for user-friendly programming and small memory use Many highly specific instructions using many addressing modes PC - program counter MAR - memory address register Address Data Main Memo ry Compact instruction codes that perform a lot of work IR - instruction register MDR - memory data register Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 15 Advanced Computer Architecture — Hadassah College — Fall 2020 Review Dr. Martin Land 16 Decoding Machine Instructions Run Time and Clock Cycles Machine Language Instruction CPU is timed by periodic signal called clock (CLK) SUB R1, R2, 100(R3) clock Microcode Instruction Sequence (Microprogram) cycle ALU_IN R3 Microcode instruction ALU 100 Hardware level atomic operation ADD 9 lines = 9 clock cycles MAR OUT Clock Cycle (CC) time = seconds per cycle READ