SystemVerilog for VHDL Users Tom Fitzpatrick Principal Technical Specialist Synopsys, Inc. Agenda • Introduction • SystemVerilog Design Features • SystemVerilog Assertions • SystemVerilog Verification Features • Using SystemVerilog and VHDL Together 2 SystemVerilog Charter • Charter: Extend Verilog IEEE 2001 to higher abstraction levels for Architectural and Algorithmic Design , and Advanced Verification. Advanced Transaction-Level V g e verification capability Full Testbench lo h A r ri c sse ilo for semiformal and Language with e en g b rt formal methods. Coverage V t io es n The Assertion T IEEE Verilog Language Standard For Verilog A I r V 2001 P c e A Design h r e i il & c Abstraction: te o fa c g I r Direct C interface, tu e Interface r DP t a n Assertion API and l I semantics, abstract Coverage API data types, abstract operators and expressions 3 SystemVerilog: Verilog 1995 Event handling Basic datatypes (bit, int, reg, wire…) Verilog-95: 4 state logic Basic programming (for, if, while,..) Single language Hardware concurrency Gate level modelling for design & design entity modularization and timing testbench Switch level modeling and timing ASIC timing 4 SystemVerilog: VHDL Operator VHDL adds Packages Overloading higher level Dynamic Simple assertions pointers data types and Architecture memory configuration management User-defined types allocation records/ functionality enums Dynamic multi-D arrays structs hardware generation Automatic variables Signed numbers Strings Event handling Basic datatypes (bit, int, reg, wire…) 4 state logic Basic programming (for, if, while,..) Hardware concurrency Gate level modelling design entity modularization and timing Switch level modeling and timing ASIC timing 5 Semantic Concepts: C Associative Operator Overloading & Sparse arrays Packages pointers Further programming Dynamic Void type (do while, memory break, continue, allocation Unions records/ ++, --, +=. etc) Simple assertions structs Strings User-defined typesenums Architecture C has extra configuration Signed numbers multi-D arrays programming features , int, reg, wire…) but lacks all hardware Dynamic Automatic variables hardware or, if, while,..) concepts generation Basic datatypes (bit 6 Basic programming (f Event handling Gate level modelling and timing 4 state logic ASIC timing Hardware concurrency design entity modularization Switch level modeling and timing SystemVerilog: Verilog-2001 Verilog-2001 adds a lot of VHDL functionality but still lacks advanced data structures Operator Packages Overloading Associative Dynamic & Sparse arrays Simple assertions pointers Architecture memory configuration User-defined types allocation Void type Further records/ programming Dynamic enums Unions multi-D arrays structs (do while, hardware break, continue, generation Strings Automatic variables Signed numbers ++, --, +=. etc) Event handling Basic datatypes (bit, int, reg, wire…) 4 state logic Basic programming (for, if, while,..) Hardware concurrency Gate level modelling design entity modularization and timing Switch level modeling and timing ASIC timing 7 SystemVerilog: Enhancements Constrained Program Clocking Enhanced Scheduling for Cycle Sequence Random Data Block Domain Testbench and Assertions Delays Events Generation Functional Sequential Semaphores Persistent Queues Classes, methods Regular events Coverage Mailboxes & inheritance Expressions Process Virtual Interface Temporal Operator Control Interfaces Specification Properties Packages Overloading Associative Dynamic & Sparse arrays Simple assertions safe pointers Architecture memory configuration User-defined types allocation Void type Further records/ programming Dynamic enums Unions multi-D arrays structs (do while, hardware g lo break, continue, generationri Automatic variables Signed numbers Strings Ve s ++, --, +=. etc) m de te vi sEventr ohandlinged dBasic datatypes (bit, int, reg, wire…) Sy p n .1 anc a 34 statev logicon Basic programming (for, if, while,..) ad ti g Packed structs ca in ifi el and unions Hardwareer concurrencyd es Gate level modelling v o ur Coverage & design mentitya tmodularization and timing C interface fe Assertion API Switch level modeling and timing ASIC timing 8 SystemVerilog: Unified Language Constrained Program Clocking Enhanced Scheduling for Cycle Sequence Random Data Block Domain Testbench and Assertions Delays Events Generation Functional Sequential Semaphores Persistent Queues Classes, methods Regular events Coverage Mailboxes & inheritance Expressions Process Virtual Interface Temporal Operator Control Interfaces Specification Properties Packages Overloading Associative Dynamic & Sparse arrays Simple assertions safe pointers Architecture memory configuration User-defined types allocation Void type Further records/ programming Dynamic enums Unions multi-D arrays structs (do while, hardware break, continue, generation Strings Automatic variables Signed numbers ++, --, +=. etc) Event handling Basic datatypes (bit, int, reg, wire…) 4 state logic Basic programming (for, if, while,..) Packed structs and unions Hardware concurrency Gate level modelling design entity modularization and timing Coverage & C interface Assertion API Switch level modeling and timing ASIC timing 9 SystemC & SystemVerilog Platform Software Based Design Transaction Level (TL) System Testbench RTL Assertions RTL Testbench RTL Gates CoverageAssertions SystemC Coverage Gates SystemVerilog …. Verilog/VHDL 10 Agenda • Introduction • SystemVerilog Design Features • SystemVerilog Assertions • SystemVerilog Verification Features • Using SystemVerilog and VHDL Together 11 Basic SystemVerilog Data Types reg r; // 4-state Verilog-2001 single-bit datatype integer i; // 4-state Verilog-2001 >= 32-bit datatype bit b; // single bit 0 or 1 logic w; // 4-valued logic, x 0 1 or z as in Verilog byte b8; // 8 bit signed integer int i; // 2-state, 32-bit signed integer Explicit 2-state Variables Allow Compiler Optimizations to Improve Performance The unresolved type “logic” in SystemVerilog is equivalent to “std_ulogic” in VHDL 12 Familiar C Features In SystemVerilog do continue starts begin next loop iteration works with: if ( (n%3) == 0 ) continue; for while if (foo == 22) break; break exits forever end the loop repeat while (foo != 0); (= “exit” in VHDL do while … Extra parentheses Blocking Assignments if ((a=b)) … required to distinguish as expressions while ((a = b || c)) from if(a==b) Auto increment/ x++; decrement operators if (--c > 17) c=0; 13 SystemVerilog Struct = Record type PKT_T is record typedef struct { PARITY: std_ulogic; logic PARITY; ADDR: std_ulogic_vector(3 downto 0); logic[3:0] ADDR; DEST: std_ulogic_vector(3 downto 0); logic[3:0] DEST; end record; } pkt_t; signal MYPKT : PKT_T; pkt_t mypkt; ... ... MYPKT.ADDR <= “1100”; mypkt.ADDR = 12; 31 3 0 The mypkt PARITY structure/ ADDR record is DEST “unpacked” In SystemVerilog, struct variables can struct { also be declared directly, without the typedef bit [7:0] opcode; bit [23:0] addr; Structure definitions are just like in C but } IR; without the optional structure tag before the ‘{‘ no typedef 14 Packed Structures and Unions typedef struct packed { typedef union packed { logic [15:0] source_port; tcp_t tcp_h; All logic [15:0] dest_port; udp_t udp_h; members logic [31:0] sequence; bit [63:0] bits; of a union } tcp_t; bit [7:0][7:0] bytes; must typedef struct packed { } ip_t; be the logic [15:0] source_port; same size logic [15:0] dest_port; logic [15:0] length; logic [15:0] checksum ip_t ip_h; } udp_t; logic parity; ip_h.udp_h.length = 5; ip_h.bits[31:16] = 5; tcp_t source_port dest_port sequence ip_h.bytes[3:2] = 5; udp_t source_port dest_port length checksum parity = ^ip_h; Equivalent Operate on entire Create multiple layouts for accessing data structure as a whole VHDL records not explicitly packed 15 Type Conversion Unpacked Structure typedef struct { logic PARITY; logic[3:0] ADDR; User-defined type: logic[3:0] DEST; packed bit vector } pkt_t; typedef bit[8:0] vec_t; pkt_t mypkt; vec_t myvec; Cast mypkt as type vec_t myvec = vec_t’(mypkt); mypkt = pkt_t’(myvec); Cast myvec as type pkt_t User-defined types and explicit casting improve readability and modularity Similar to Qualified Expressions or conversion functions in VHDL 16 Data Organization - Enum VHDL: SystemVerilog: type FSM_ST is typedef enum logic [2:0] {IDLE, {idle,idle = 0, INIT, init,init = 3, DECODE, decode, // = 4 …}; …} fsmstate; signal pstate, nstate : FSM_ST; fsmstate pstate, nstate; case (pstate) is case (pstate) when idle: idle: if (sync) if (sync = ‘1’) then nstate = init; nstate <= init; init: if (rdy) end if; nstate = decode; when init: if (rdy = ‘1’) then … nstate = decode; endcase end if; … end case; VHDL enums not explicitly typed 17 Packed and Unpacked Arrays unpacked bit a [3:0]; a0 array of bits a1 a2 a3 Don’tDon’t get get them them mixed mixed up up unused packed bit [3:0] p; array of p3 p2 p1 p0 bits 1k 16 bit unpacked bit [15:0] memory [1023:0]; memory memory[i] = ~memory[i]; Packed memory[i][15:8] = 0; indexes can be 1k 16 bit sliced packed bit [15:0][1023:0] Frame; always @inv Frame = ~Frame; Can operate on memory entire memory SystemVerilog also includes the VHDL-like array attribute functions: $left, $right, $low, $high, $increment, $length and $dimensions 18 Pre-Post Synthesis Mismatches RTL Synthesis Gates =/ • Causes • Sensitivity list mismatches • Pragmas affect synthesis but not simulation • SystemVerilog Solves these problems • Specialized always blocks automate sensitivity • Synthesis directives built into the language 19