DEC 7000/10000 AXP KN7AA CPU Technical Manual Order Number EK—KN7AA—TM.001 The KN7AA is an Alpha AXP CPU module designed for the LSB platform. It is based on the DECchip 21064 microprocessor and is used in the DEC 7000 and DEC 10000 RISC systems. It supports up to seven MS7AA memory mod- ules in a uniprocessor configuration and one IOP module per system. A multiprocessor system can be configured by either loading additional modules in empty backplane slots or replacing a memory module with a CPU module. digital equipment corporation maynard, massachusetts First Printing, July 1993 The information in this document is subject to change without notice and should not be construed as a com- mitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. The software, if any, described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license. No responsibility is assumed for the use or reliability of soft- ware or equipment that is not supplied by Digital Equipment Corporation or its affiliated companies. Copyright © 1993 by Digital Equipment Corporation. All Rights Reserved. Printed in U.S.A. The following are trademarks of Digital Equipment Corporation: Alpha AXP DECUS VAXBI AXP DWMVA VAXELN DEC OpenVMS VMScluster DECchip ULTRIX XMI DEC LANcontroller UNIBUS The AXP logo DECnet VAX dT OSF/1 is a registered trademark of the Open Software Foundation, Inc. FCC NOTICE: The equipment described in this manual generates, uses, and may emit radio frequency en- ergy. The equipment has been type tested and found to comply with the limits for a Class A computing de- vice pursuant to Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection against such radio frequency interference when operated in a commercial environment. Operation of this equipment in a residential area may cause interference, in which case the user at his own expense may be required to take measures to correct the interference. Contents Preface ............................................................................................................................................. xi Chapter 1 KN7AA CPU Module Overview 1.1 DECchip 21064.............................................................................................................. 1-2 1.2 Backup Cache (B-Cache) .............................................................................................. 1-3 1.3 LSB Interface (LEVI) ................................................................................................... 1-3 Chapter 2 Address Space 2.1 Memory Space Map ....................................................................................................... 2-1 2.2 I/O Space Map ............................................................................................................... 2-2 2.2.1 LSB CSR Map ......................................................................................................... 2-2 2.2.2 Gbus Map ................................................................................................................ 2-3 2.2.3 Broadcast Space ...................................................................................................... 2-4 Chapter 3 Alpha AXP Architecture Overview 3.1 Data Types..................................................................................................................... 3-1 3.2 Instructions ................................................................................................................... 3-2 3.2.1 Instruction Format Classes.................................................................................... 3-2 3.2.2 Instruction Set Characteristics.............................................................................. 3-3 3.3 Architecturally Defined OpenVMS AXP IPRs ............................................................ 3-4 Chapter 4 DECchip 21064 Overview 4.1 Functional Units ........................................................................................................... 4-2 4.1.1 Ibox .......................................................................................................................... 4-2 4.1.1.1 Branch Prediction Logic .................................................................................. 4-3 4.1.1.2 Instruction Translation Buffers ...................................................................... 4-3 4.1.1.3 Interrupt Logic ................................................................................................. 4-4 4.1.1.4 Performance Counters ..................................................................................... 4-5 4.1.2 Ebox ......................................................................................................................... 4-6 4.1.3 Abox ......................................................................................................................... 4-6 4.1.3.1 Data Translation Buffer .................................................................................. 4-6 4.1.3.2 Bus Interface Unit .......................................................................................... 4-7 4.1.3.3 Load Silos ......................................................................................................... 4-7 4.1.3.4 Write Buffer...................................................................................................... 4-8 4.1.4 Fbox ......................................................................................................................... 4-9 4.1.4.1 Operation .......................................................................................................... 4-9 iii 4.1.4.2 IEEE Floating-Point Conformance ............................................................... 4-10 4.2 Internal Cache ............................................................................................................ 4-11 4.3 Pipeline Organization ................................................................................................. 4-11 4.3.1 Static and Dynamic Stages .................................................................................. 4-13 4.3.2 Aborts .................................................................................................................... 4-13 4.3.3 Nonissue Conditions ............................................................................................. 4-14 4.4 Scheduling and Issuing Rules .................................................................................... 4-14 4.4.1 Instruction Class Definition................................................................................. 4-14 4.4.2 Producer-Consumer Latency ............................................................................... 4-15 4.4.3 Instruction Issue Rules ........................................................................................ 4-17 4.4.4 Dual-Issue Table ................................................................................................... 4-18 4.5 PALcode Instructions.................................................................................................. 4-19 4.5.1 Required PALcode Instructions .......................................................................... 4-19 4.5.2 PALcode Instructions That Require Recognition ............................................... 4-20 4.5.3 Architecturally Reserved PALcode Instructions................................................. 4-20 4.6 Exceptions and Interrupts .......................................................................................... 4-21 4.6.1 Exceptions ............................................................................................................. 4-21 4.6.2 Interrupts .............................................................................................................. 4-22 4.7 Internal Processor Registers ...................................................................................... 4-23 4.7.1 IPR Access ............................................................................................................. 4-23 4.7.2 IPR Descriptions ................................................................................................... 4-27 TB_TAG—Translation Buffer Tag Register........................................................ 4-29 ITB_PTE—Instruction Translation Buffer PTE Register .................................. 4-30 ICCSR—Instruction Cache Control/Status Register .......................................... 4-31 ITB_PTE_TEMP—Instruction Translation Buffer PTE_TEMP Register......... 4-36 EXC_ADDR—Exception Address Register ......................................................... 4-37 SL_RCV—Serial Line Receive Register .............................................................. 4-39 PS—Processor Status Register ........................................................................... 4-40 EXC_SUM—Exception Summary Register......................................................... 4-41 PAL_BASE—PALcode Base Address Register ................................................... 4-43 HIRR—Hardware Interrupt Request Register ................................................... 4-44 SIRR—Software Interrupt Request Register ...................................................... 4-46 ASTRR—Asynchronous Trap Request Register ................................................. 4-47