SIGARCH Visioning Workshop @ ISCA 2019 The Four Steps to Open-Source Chip Ecosystem Yungang Bao ICT, CAS Pengcheng Laboratory 2019-6-23 The Journey of A Research Project NSFC ASPLOS MOST Labeled Mini An Idea Funding Paper Funding RISC-V FPGA-Cloud Labeled Computer 2012 2013 2014 2015 2016 2017 2018 Architecture https://github.com/LvNA Attempt 1 -system/labeled-RISC-V/ Sparc T1 Attempt 2 MicroBlaze Experience in Attempt 3 RISC-V and RISC-V chip agile development Computer = Network • Communication via internal packets • e.g., PCIe, NoCs, QPI Ma et al., Supporting Differentiated Services in Computers via Programmable Architecture for Resourcing-on-Demand (PARD). ASPLOS, 2015. Computer → SDN ? • Enable research on architectural support for QoS/Security/… Software-Defined Architecture Software-Defined Networking Application Layer 策略 Application策略 Control Layer 策略策略Control V. Policy S. Hardware Layer Image Source: https://www.mdpi.com/1999-5903/6/2/302 Labeled RISC-V Mini FPGA-Cloud • SoC: 4/8 core, 16-way L2$, • FPGA as a Service DRAM Ctrler, GbE, … • A cluster of – • Scalable for multiple FPGAs 8 FPGAs for research – 32 FPGAs for education contact [email protected] for FREE use Yu et al.,, Labeled RISC-V: A New Perspective on Zhang et al., Computer Organization and Design Software-Defined Architecture. CARRV, 2017 Course with FPGA Cloud, SIGCSE, 2019. Tutorial @ MICRO 2018 • http://sdc.ict.ac.cn/micro2018-tutorial/ Open-Sourced Codes @ Github • https://github.com/LvNA-system/labeled-RISC-V/ Open-source chip design ecosystem & Status in China NSFC ASPLOS MOST Labeled Mini An Idea Funding Paper Funding RISC-V FPGA-Cloud Labeled Computer 2012 2013 2014 2015 2016 2017 2018 Architecture https://github.com/LvNA Attempt 1 -system/labeled-RISC-V/ Sparc T1 Attempt 2 MicroBlaze Experience in Attempt 3 RISC-V and RISC-V chip agile development Open-Source Software Ecosystem • Lower barrier of innovation – Develop an App by 3-5 engineers within 3-5 months Customized codes < 10% LOC LAMP/MEAN etc. > 90% LOC High Barrier of Chip Development • Ex: 7nm technology requires $100M and 100X man-years • Only very few companies can afford • High barrier to innovations Source: Andreas Olofsson, Intelligent Design of Electronic Assets (IDEA),2017 Open-Source Chip: The DEADLOCK to be broken Unwilling to Large dev. cost open source Reduce risks by long- No open- time verification source choices Buy high price IPs Opportunities • Bell’s Law is still alive: New requirements on IoT chips – E.g. customizable design, small size, fast TTM, low power, low cost, new programming paradigm, low-end manufacture technology etc. • Moore’s Law is ending: The cost of mature process technology (e.g. 40nm) is stepping down • A golden era is coming: Chemical reactions occur while blending – free ISAs, open-source gadgets, new languages, emerging applications, clouds etc. % of Academia papers on ISSCC 180 60.0% 53.2% 160 140 120 40.0% 30.6% IoT 100 80 15.8% 60 20.0% 40 10.7% 20 0 0.0% 1988 1998 2008 2018 Academia Only Industry & Others Rate Image Source: https://www.computerhistory.org/atchm/the-worlds-smallest-computer/ Four Steps (Pillars) • An open source chip ecosystem (OSCE) save time- to-market and the cost of IPs, EDA tools, facilities and labors. Customized codes < 10% LOC Open Source Chip Ecosystem OS/Compiler Verification/ Languages/ Simulation EDA tools ISAs/IPs/ SoCs > 90% LOC Platform ISA, IP & SoC • ISA: RISC-V lays a foundation • IP & SoC: Still lack high-perf and for OSCE high-quality open IPs & SoCs – Two RISC-V alliances in China: – Should be verified by tapeout CRVA, CRVIC – Hummingbirds E200 RISC-V (core), – About 200 members in total Labeled RISC-V (SoC) – More on-going open source IPs Image Source: http://crva.io/ , http://www.sohu.com/a/255272568_177021 , GitHub RIOS Laboratory at Tsinghua-Berkeley Shenzhen Institute (TBSI) • On June 12th, Prof. David Patterson announced to establish a RISC-V International Open Source Laboratory (RIOS Laboratory) in Shenzhen, China, which will focus on “uncore” IPs Image Source: https://news.tsinghua.edu.cn/publish/thunewsen/9671/2019/20190618100437508992356/20190618100437508992356_.html Languages, EDA tools • Languages: Higher abstraction languages improve productivity by 10X – Chisel, PyMTL, … • EDA Tools: A number of open source EDA gadgets already exist Front End: Design NetList Language Synthesis Simulator Verification Verilog, Chisel, PyMTL, Icarus Verilog, Yosys, abc RISCV-DV VHDL PyRTL, MyHDL Verilator Tool Chain Qflow, Back End: NetList GDS Layout OpenRoad, VSD Placement Routing Static Timing Analysis Layout Graywolf, Qrouter, OpenTimer, Magic, RePLAce FGR OpenSTA Taped A tale of two languages (in our lab) Verilog versus Chisel ⚫ Task #1: Design an L2 Cache for RISC-V Rocket-chip core ⚫ Who: A 5-year engineer vs. a senior student A 5-year Engineer An Undergraduate Familiar w/ OpenSparc T1; Course projects on CPU design; Experience Modified Xilinx Cache Using Chisel for 9 months Language Verilog Chisel Time 6 weeks 3 days LOCs ~1700 ~350 Boot Linux on multicore RISC-V; Results Unable to boot Linux support NIC w/ DMA mode ⚫ 1st Round results: Chisel is more productive than Verilog by 14X with only 1/5 LOC PPA: Chisel versus Verilog • Task #2: Translate the Verilog codes into Chisel – Evaluated on FPGA (xc7v2000tfhg1716-1), Vivado 2017.01 • Who: A junior student who never knew Chisel Chisel Chisel-opt Verilog (direct translation) (adv. features & libs) Freq./MHz 135.814 136.388 (+0.42%) 154.107 (+13.47%) Power/W 0.770 0.749 (-2.73%) 0.749 (-2.73%) LUT Logic 5676 6422 (+13.14%) 2594 (-54.30%) LUT Storage 1796 1264 (-29.62%) 1492 (-16.93%) FF 4266 3638 (-14.72%) 747 (-82.49%) LOCS 618 470 (-23.95%) 155 (-74.92%) ⚫ 2nd Round results: Chisel can achieve better PPA than verilog Yu et al., Practice of Chip Agile Development: Labeled RISC-V, Journal of Computer Research and Development, 2019, 56(1): 35-48. Dawning of open-source EDA tools • Task: Generate GDSII from RTL fully by open source EDA tools – A MCU-level RISC-V core + Qflow + SIMC 180nm • Who: A software programmer who never knew EDA • Results: The complete open-source design flow works. But still need stable, fast, high-quality and well-maintained toolchain distributions – Like Debian, Fedora and Ubuntu for Linux RTL of an open-source GDSII RISC-V core (E203) w/ SIMC 180nm Verification, Simulation • Cloud-based verification & simulation: Lower the barrier of verification and simulation by pay-as-you-go mode rather than buying very expensive facilities and servers – FireSim, Alibaba’s Pingtouge, … • Practice in UCAS: Satisfaction Survey Build an FPGA mini-cloud FPGA Board FPGA Cloud for labs of undergraduate (2017) (2018) COD course 26.8% 87.8% – Serve ~200 students since 2018 – Survey: 34.8% of students turned from “unlike” to “like” system design Please contact [email protected] for FREE use Zhang et al., Computer Organization and Design Course with FPGA Cloud, SIGCSE, 2019. SW toolchain: OS, Compiler, … • Three layers of SW support are needed – Chip-oriented (Linux, LLVM): extended ISA, sensor drivers etc. – Function SW (Linaro): languages, libraries, JVM, DBMS etc. – User/Programmer-oriented (Android): APIs, UI etc. Image Source: http://events17.linuxfoundation.org/sites/events/files/slides/From%2096Boards%20to%20the%20Cloud.pdf Just like we were in the mid-1990s of open-source SW era • OSCE looks exciting in the future, but still has a long way to go • ICT and Pengcheng Laboratory have launched Open Chip Lab – Building an open-source chip platform for education Open Source Chip Ecosystem Long way to go Chisel/ RISC Qflow Linux/ LLVM Cloud FPGA - V Open ChipPlatform Lab @ ICT+PCL Envision: Designless Mode • Designless: design chips w/o IC design expertise • Make designing a chip like designing a mobile app Courtesy: Dr. Yunlong Zheng, Shanghai Institute of Microsystem and Information Technology (SIMIT), Chinese Academy of Sciences Conclusion It is time to break the deadlock of open-source chip 23 Acknowledgements • ICT Director • Some members of Open Chip Lab • Prof. Ninghui Sun • Yungang Bao, Yisong Chang, Dejung Jiang, Dan Tang, Biwei Xie, Sa Wang, Zihao Yu, Ke Zhang, Ran Zhao Thanks 谢谢！.