L- and H-Tile Transceiver PHY User Guide Subscribe UG-20055 | 2021.09.09 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Overview........................................................................................................................ 7 1.1. L-Tile/H-Tile Layout in Intel Stratix 10 Device Variants................................................ 8 1.1.1. Intel Stratix 10 GX/SX H-Tile Configurations..................................................8 1.1.2. Intel Stratix 10 TX H-Tile and E-Tile Configurations....................................... 10 1.1.3. Intel Stratix 10 MX H-Tile and E-Tile Configurations...................................... 12 1.2. L-Tile/H-Tile Counts in Intel Stratix 10 Devices and Package Variants.......................... 14 1.3. L-Tile/H-Tile Building Blocks...................................................................................16 1.3.1. Transceiver Bank Architecture....................................................................17 1.3.2. Transceiver Channel Types........................................................................ 17 1.3.3. GX and GXT Channel Placement Guidelines..................................................19 1.3.4. GXT Channel Usage..................................................................................19 1.3.5. PLL and Clock Networks............................................................................ 20 1.3.6. Ethernet Hard IP......................................................................................23 1.3.7. PCIe Gen1/Gen2/Gen3 Hard IP Block..........................................................25 1.4. Overview Revision History.....................................................................................29 2. Implementing the Transceiver PHY Layer in L-Tile/H-Tile............................................ 31 2.1. Transceiver Design IP Blocks................................................................................. 31 2.2. Transceiver Design Flow........................................................................................32 2.2.1. Select the PLL IP Core.............................................................................. 32 2.2.2. Reset Controller ......................................................................................33 2.2.3. Create Reconfiguration Logic..................................................................... 33 2.2.4. Connect the Native PHY IP Core to the PLL IP Core and Reset Controller.......... 33 2.2.5. Connect Datapath ................................................................................... 34 2.2.6. Modify Native PHY IP Core SDC..................................................................34 2.2.7. Compile the Design.................................................................................. 34 2.2.8. Verify Design Functionality........................................................................ 34 2.3. Configuring the Native PHY IP Core........................................................................ 35 2.3.1. Protocol Presets.......................................................................................36 2.3.2. GXT Channels..........................................................................................37 2.3.3. General and Datapath Parameters ............................................................. 37 2.3.4. PMA Parameters...................................................................................... 40 2.3.5. PCS-Core Interface Parameters..................................................................43 2.3.6. Analog PMA Settings Parameters................................................................48 2.3.7. Enhanced PCS Parameters ........................................................................54 2.3.8. Standard PCS Parameters......................................................................... 58 2.3.9. PCS Direct Datapath Parameters............................................................... 62 2.3.10. Dynamic Reconfiguration Parameters........................................................ 62 2.3.11. Generation Options Parameters................................................................ 65 2.3.12. PMA, Calibration, and Reset Ports............................................................. 65 2.3.13. PCS-Core Interface Ports.........................................................................68 2.3.14. Enhanced PCS Ports............................................................................... 75 2.3.15. Standard PCS Ports................................................................................ 81 2.3.16. Transceiver PHY PCS-to-Core Interface Reference Port Mapping.................... 87 2.3.17. IP Core File Locations............................................................................105 2.4. Using the Intel Stratix 10 L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10 FPGA IP Core.......................................................................................................... 107 L- and H-Tile Transceiver PHY User Guide Send Feedback 2 Contents 2.4.1. PMA Functions....................................................................................... 109 2.4.2. PCS Functions........................................................................................111 2.4.3. Deterministic Latency Use Model.............................................................. 146 2.4.4. Debug Functions.................................................................................... 154 2.5. Implementing the PHY Layer for Transceiver Protocols.............................................165 2.5.1. PCI Express (PIPE)................................................................................ 165 2.5.2. Interlaken............................................................................................ 216 2.5.3. Ethernet............................................................................................... 223 2.5.4. CPRI....................................................................................................229 2.6. Unused or Idle Transceiver Channels.....................................................................235 2.7. Simulating the Native PHY IP Core........................................................................238 2.7.1. How to Specify Third-Party RTL Simulators ............................................... 238 2.7.2. Scripting IP Simulation............................................................................240 2.7.3. Custom Simulation Flow..........................................................................242 2.8. Implementing the Transceiver Native PHY Layer in L-Tile/H-Tile Revision History......... 245 3. PLLs and Clock Networks............................................................................................ 252 3.1. PLLs................................................................................................................. 254 3.1.1. ATX PLL................................................................................................ 254 3.1.2. fPLL......................................................................................................269 3.1.3. CMU PLL............................................................................................... 276 3.2. Input Reference Clock Sources............................................................................281 3.2.1. Dedicated Reference Clock Pins............................................................... 282 3.2.2. Receiver Input Pins.................................................................................284 3.2.3. PLL Cascading as an Input Reference Clock Source..................................... 285 3.2.4. Reference Clock Network.........................................................................285 3.2.5. Core Clock as an Input Reference Clock.....................................................285 3.3. Transmitter Clock Network...................................................................................286 3.3.1. x1 Clock Lines....................................................................................... 286 3.3.2. x6 Clock Lines....................................................................................... 287 3.3.3. x24 Clock Lines......................................................................................289 3.3.4. GXT Clock Network.................................................................................292 3.3.5. HCLK Network....................................................................................... 294 3.4. Clock Generation Block....................................................................................... 295 3.5. FPGA Fabric-Transceiver Interface Clocking............................................................ 297 3.6. Double Rate Transfer Mode..................................................................................298 3.7. Transmitter Data Path Interface Clocking...............................................................298 3.8. Receiver Data Path Interface Clocking...................................................................300 3.9. Channel Bonding................................................................................................302 3.9.1. PMA Bonding......................................................................................... 302 3.9.2. PMA and PCS Bonding.............................................................................303