Common Gate Stage Cascode Stage Claudio Talarico, Gonzaga University Common Gate Stage The overdrive due to VB must be “consistent” careful with signs: with the current pulled by the DC source IB vgs = vbs = -vi VDD R RLD R RLD Vo Cgd+Cdb Vo V B G & B D (grounded) -(g +g )v m mb i ro S + i R IB i CSi i R C +C +C i RSi vi gs sb i Ri - Driving Circuit (e.g. photodiode) Define: CS = Cgs +Csb +Ci g'm = gm + gmb CD = Cgd +Cdb “enhanced” gm’ Ri models finite resistance in the driving circuit due to both “gates” Ci models parasitic capacitance in the driving circuit EE 303 – Common Gate Stage 2 Common Stage Bias Point Analysis § Assume Ri is large: (very reasonable for a reverse biased photodiode) 1 W I ≅ I = µC (V −V )2 V = V +γ PHI +V − PHI B D 2 OX L GS t t t0 ( SB ) ID≅IB VSB = VS VOUT = VDD − RDIB I V B DD VGS = Vt + 0.5µCOXW / L A precise solution requires RD VOUT numerical iterations. Since IB the dependency of V on V VS = VB −VGS = VB −Vt − t S 0.5µCOXW / L is weak a few iterations are VB satisfactory for hand calculation VS Once VS is computed we can check that M1 operates in saturation: Ri IB VDS = VOUT −VS > VDsat = VGS −Vt EE 303 – Common Gate Stage 3 CG biasing (1) § Example: VDD = 5V; VB = 2.5V; IB = 400µA; RD=3KΩ; W=100µm; L=1µm; Vt0 = 0.5V * CG stage * filename: cgbias.sp element 0:mn1 * C. Talarico, Fall 2014 model 0:simple_n region Saturati *** device model id 400.0000u .model simple_nmos nmos kp=50u vto=0.5 lambda=0.1 cox=2.3e-3 capop=2 ibs -13.0770f + cgdo=0.5n cgso=0.5n cj=0.1m cjsw=0.5n pb=0.95 mj=0.5 mjsw=0.95 ibd -38.0000f + acm=3 cjgate=0 hdif=1.5u gamma=0.6 PHI=0.8 vgs 1.1923 vds 2.4923 *** useful options vbs -1.3077 .option post brief nomod accurate vth 834.4189m vdsat 357.8811m *** circuit vod 357.8811m VDD vdd 0 5 beta 6.2462m * IB vi 0 dc 400u gam eff 600.0000m VS vi 0 dc 1.3077 *** value for .op analysis gm 2.2354m VB vb 0 dc 2.5 gds 32.0197u *** d g s b gmb 461.9214u mn1 vo vb vi 0 simple_nmos w=100u l=1u cdtot 75.6690f Rd vdd vo 3k cgtot 256.1831f *** calculate operating point cstot 246.0823f .op cbtot 69.7376f *** large signal analysis (sweep Vi) cgs 203.3341f .dc VS 0 5 0.01 cgd 50.7643f! .end ! EE 303 – Common Gate Stage 4 CG biasing (2) DC Transfer Function − 1 um Technology 5.5 M1 cut-off 5 4.5 4 3.5 M1 saturation 3 [V] out 2.5 V 2 1.5 1 M1 triode 0.5 0 0 0.5 1 1.5 2 2.5 3 V =V [V] in s VB-Vt § The I/O characteristic is flipped w.r.t. the CS stage (small signal voltage gain AV = dVout/dVin is positive !) EE 303 – Common Gate Stage 5 CG small signal model § Depending on how the CG is used the output variable of interest may be: - The current that flows into the output (Current Buffer) - The voltage at the output (Transresistance Amplifier) D careful with signs: vout vbs=vgs = -vs CD RD gmbvbs gmvgs G G& B ro R 1 S Z = D = D 1 vs 1+ sRDCD sCD + RD i C s rRs s S R 1 Z = S = S 1 1+ sRSCS sCS + EE 303 – Common Gate Stage RS 6 CG input impedance (1) First pass: ZS in || to vtest so let’s temporarily “remove” it i o = itest w.r.t. (g’ r >> 1) KCL@vo : m o vo vo vtest + 0 = + − − g'm vtest ⇒ vo ≅ g'm (ZD || ro )vtest g’ v = g’g' vv v Z r r m s mm testgs ro o RZLD D o o CS - S KCL@v : test w.r.t. (g’mro >> 1) + vgs - Y v v in i = g' v + test − o v test m test test ro ro Aside: if g’ r is not >> 1 m o i Z r g' r test g' g' D o m o Z ≅ m − m = 1+ D vtest ro (ZD + ro ) ZD + ro v r test = o i 1 test g' + m r o EE 303 – Common Gate Stage 7 CG input impedance (2) Final Pass: Let’s bring back ZS: i o = itest g'm ro 1 g'm ro 1 + Y ≅ + sC + = + sC + g’ v = g’ v in S " % S m s mg' testv v ZD + ro RS 1 RS m gs ro o RZLD C $RD || '+ ro ZSs - # sCD & S + vgs - Yin v test " 1 % ro +$RD || ' # sCD & 1 Zin ≅ || || RS g'm ro sCS g’mro >> 1 (always true with our technology !!) EE 303 – Common Gate Stage 8 CG input impedance: Summary (1) " 1 % ro +$RD || ' # sCD & 1 Zin ≅ || || RS g'm ro sCS ro + RD § At low frequency: Rin ≅ || RS g'm ro § Two interesting cases: Typically R >> 1/g’ S m Well known 1 - RD << ro Rin ≅ || RS If not most of the driving result ! g'm current instead of going to the MOS is lost !! This happen quite often !! Not so Well - RD is not << ro (example: RD is a current source load) known … EE 303 – Common Gate Stage 9 CG input impedance: Summary (2) " 1 % ro +$RD || ' # sCD & 1 Zin ≅ || || RS g'm ro sCS § At high frequency - As long as RD << ro (regardless of the term CD) Typically R >> 1/g’ S m NOTE: 1 1 1 1 1 Zin ≅ || || RS ≅ || R D | | is always < than RD. g'm sCS g'm sCS sC D 1 If RD << ro so is RD || sCD EE 303 – Common Gate Stage 10 CG output impedance (1) w.r.t. (g’mro >> 1) § At low frequency vtest vs itest = − − g'm vs R r r D out o o itest vs = RS ⋅itest -g' v g’mmgvss ro vtest CS S vtest + vgs - R = ≅ r (1+ g' R ) R out o m S S itest G & B (Very high if g’mRS >> 1) Aside: if g’ r is not >> 1 m o vtest Rout = ≅ rog'm RS vtest itest Rout = = RS + ro (1+ g'm RS ) itest EE 303 – Common Gate Stage 11 CG output impedance (2) § At high frequency R D out itest -gg’' vv ( " 1 %+ 1 mm gss ro vtest Zout ≅ ro *1+ g'm $RS || '-|| CS CD ) # sCS &, sCD S + v - CgSs RS G & B Typically CS/(g’mro) << CD g'm ro 1 1 If g’mRs >> 1 Zout ≅ g'm roRS || || ≅ g'm roRS || sCs sCD sCD EE 303 – Common Gate Stage 12 CG current transfer (1) RS RS w.r.t. (g’mro >> 1) vs vout RDiout iout = − + g'm vs ≅ − + gm 'vs ro ro ro RS ! $ RD iout iout #1+ & ≅ g'm vs " ro % NOTE : for ro >> RD → iout ≅ gm 'vs The CG stage is approx. unilateral EE 303 – Common Gate Stage 13 CG current transfer (2) iin=g’mvs RS CG stage model valid for: g’ v m s g’mro >> 1 and ro >> RD iout § At low frequency: - for g’mro >> 1 and ro >> RD) i i i R out = out in ≅ S ≅1 This is a current buffer !!! 1 is iin is AI0 ≅1, Rin small, Rout large + RS g'm Typically g’mRS >>1 EE 303 – Common Gate Stage 14 CG current transfer (3) Zin* CG Core Zout ro iout vs vout is rRs S 1/g’m RD Cgs+Csb Cgd+Cdb g’mvs i io Cs in Cd § At high frequency: ! 1 $ since R > R || , r >> R implies r >> Z - for g’mro >> 1 and ro >> RD # D D o D o D & " sCD % i g' v g' R A g' R 1 o ≅ m s = m S = I 0 = m S ⋅ i " % 1 sR C g' R s 1 g' R CS s 1 + S S + m S 1− + m S 1+ s $ + sCS + g'm 'vs 1 R p1 # S & g'm + RS EE 303 – Common Gate Stage 15 CG current transfer (4) Zin* CG Core Zout ro iout vs vout is rRs S 1/g’m RD Cgs+Csb Cgd+Cdb g’mvs i io Cs in Cd 1 i i i sC g' R 1 1 g' R 1 out = out o ≅ D ⋅ m S ⋅ = ⋅ m S ⋅ i i i 1 1+ g' R CS 1+ sC R 1+ g' R CS s o s + R m S 1+ s D D m S 1+ s D 1 1 sCD g'm + g'm + RS RS 1 AI0 i 1 s out ≅ 1− i " C % p 1 s 1 sC R 1 s S 2 ( + D D )$ + ' s # g'm & 1− p Typically g’mRS >>1 1 EE 303 – Common Gate Stage 16 CG Input-Output RC Time Constants io + g' v r v R C m gs o >>o RLD D CS - + vgs - Yin v itSes t RS § For this specific configuration and assumptions (ro >> RD and g’mro >>1) input and output are decoupled à “RC time constants” are = 1/poles - Input RC: ~CS(1/g’m) (RS>>1/g’m) - Output RC: RDCD EE 303 – Common Gate Stage 17 CG Frequency Response AC response − CS stage vs. CG stage 40 10.07 ( 20.06 dB) 20 3.39GHz 7.85 (17.89 dB) 124.27 MHz 0 −20 Gain [dB] −40 −60 CS stage CG stage −80 5 6 7 8 9 10 11 12 10 10 10 10 10 10 10 10 freq [Hz] ≅ Av0_CS ≅ − gmRD Av0_CG g’mRD EE 303 – Common Gate Stage 18 CG Summary § Current gain is about unity up to very high frequencies - The CG stage absorbs most of the current from the input source and it passes the current to the output terminal § The CG does not contain a FB capacitance between input and output (no Miller effect) - The effect of large values of RD on the frequency response in much less than in CS stage (for a desired BW we can extract more gain out of the CG stage) § Input impedance is “typically” very low (Rin ≅ 1/g’m) – At least when the output is terminated with some reasonable impedance (RD << ro) § Can achieve very high output resistance (Rout ≈ rog’mRS) § In summary, a common gate stage is ideal for turning a decent current source into a much better one – Seems like this is something we can use to improve our common source stage • Which is indeed nothing but a decent (voltage controlled) current source EE 303 – Common Gate Stage 19 “Aside” § If we cannot assume ro>>RD, the unilateral model used for the CG stage falls apart.