Phase Locked Loop Design as a Frequency Multiplier A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Technology in VLSI Design and Embedded System By GEORGE TOM VARGHESE ROLL No: 207EC204 Department of Electronics and Communication Engineering National Institute Of Technology Rourkela 2007-2009 Phase Locked Loop Design as a Frequency Multiplier A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Technology in VLSI Design and Embedded System By GEORGE TOM VARGHESE ROLL No: 207EC204 Under the Guidance of Prof. KAMALAKANTA MAHAPATRA Department of Electronics and Communication Engineering National Institute Of Technology Rourkela 2007-2009 National Institute Of Technology Rourkela CERTIFICATE This is to certify that the thesis entitled, “Phase Locked Loop Design As A Frequency Multiplier” submitted by George Tom Varghese in partial fulfillment of the requirements for the award of Master of Technology Degree in Electronics & Communication Engineering with specialization in “VLSI Design and Embedded System” at the National Institute of Technology, Rourkela (Deemed University) is an authentic work carried out by him under my supervision and guidance. To the best of my knowledge, the matter embodied in the thesis has not been submitted to any other University / Institute for the award of any Degree or Diploma. Date: Prof. K. K. Mahapatra Dept. of Electronics & Communication Engg. National Institute of Technology Rourkela-769008 ACKNOWLEDGEMENTS This project is by far the most significant accomplishment in my life and it would be impossible without people (especially my family) who supported me and believed in me. I am thankful to Dr. K. K. Mahapatra, Professor in the department of Electronics and Communication Engineering, NIT Rourkela for giving me the opportunity to work under him and lending every support at every stage of this project work. I truly appreciate and value him esteemed guidance and encouragement from the beginning to the end of this thesis. I am indebted to his for having helped me shape the problem and providing insights towards the solution. His trust and support inspired me in the most important moments of making right decisions and I am glad to work with him. I want to thank all my teachers Prof. S.K. Patra, Prof. G.Panda, Prof. G.S. Rath, Prof. S. Meher, and Prof. D.P.Acharya for providing a solid background for my studies and research thereafter. I also very thankful to all my class mates and seniors of VLSI lab-I especially Sushant Pattnaik, Dr. Jitendra K Das, Swain Ayas Kanta and K Sudeendra Kumar who always encouraged me in the successful completion of my thesis work. GEORGE TOM VARGHESE ROLL No: 207EC204 i CONTENTS ABSTRACT ...........................................................................................................................................IV LIST OF FIGURES ................................................................................................................................. V ABBREVIATIONS USED ....................................................................................................................VII INTRODUCTION ......................................................................................................................1 1.1 MOTIVATION .................................................................................................................................. 2 1.2 SYSTEM OVERVIEW ........................................................................................................................ 2 1.3 APPLICATIONS ................................................................................................................................ 4 1.4 LITERATURE REVIEW ...................................................................................................................... 4 PHASE FREQUENCY DETECTOR ..........................................................................................6 2.1 INTRODUCTION ............................................................................................................................... 7 2.2 PHASE DETECTOR AND PHASE FREQUENCY DETECTOR ................................................................... 7 2.3 LOW GLITCH HIGH SPEED CMOS PHASE FREQUENCY DETECTOR ................................................. 12 2.4 CHARACTERISTICS OF PFD ........................................................................................................... 17 CHARGE PUMP ...................................................................................................................... 21 3.1 INTRODUCTION ............................................................................................................................. 22 3.2 CHARGE PUMP CONFIGURATION ................................................................................................... 24 3.3 MODIFIED CHARGE PUMP ............................................................................................................. 27 LOOP FILTER ......................................................................................................................... 29 4.1 INTRODUCTION ............................................................................................................................. 30 4.2 TRANSFER FUNCTION OF PFD/CP/LPF .......................................................................................... 31 4.3 ADDITION OF RESISTANCE INTO THE LOOP FILTER ........................................................................ 34 4.4 ADDITION OF SECOND CAPACITOR INTO THE LOOP FILTER............................................................ 37 VOLTAGE CONTROLLED OSCILLATOR & DIVIDE BY COUNTER ................................ 38 ii 5.1 INTRODUCTION ............................................................................................................................... 39 5.2 CURRENT STARVED VCO ............................................................................................................. 41 5.3 PLL SPECIFICATIONS .................................................................................................................... 44 5.4 DIVIDE BY COUNTER..................................................................................................................... 45 5.5 PHASE LOCKED LOOP ................................................................................................................... 46 APPLICATIONS OF PLL & CONCLUSIONS ......................................................................... 48 6.1 CLOCK RECOVERY ........................................................................................................................ 49 6.2 CLOCK GENERATION .................................................................................................................... 49 6.3 FREQUENCY SYNTHESIS ................................................................................................................ 49 6.4 CONCLUSIONS .............................................................................................................................. 50 REFERENCES...................................................................................................................................... 51 LAYOUTS ............................................................................................................................................ 54 iii ABSTRACT High-performance digital systems use clocks to sequence operations and synchronize between functional units and between ICs. Clock frequencies and data rates have been increasing with each generation of processing technology and processor architecture. Phase locked-loops (PLLs) are widely used to generate well-timed on-chip clocks in high-performance digital systems. A PLL is a closed loop frequency system that locks the phase of an output signal to an input reference signal. PLL‘s are widely used in computer, radio, and telecommunications systems where it is necessary to stabilize a generated signal or to detect signals. The term ―lock‖ refers to a constant or zero phase difference between two signals. The signal from the feedback path f D is compared to the input reference signal, f IN until the two signals are locked. If the phase is unmatched, this is called the unlocked state, and the signal is sent to each component in the loop to correct the phase difference. These components consist of the Phase Frequency Detector (PFD), the charge pump (CP), the low pass filter (LPF), the voltage controlled oscillator (VCO) and divide by counter. The PFD detects any phase differences in and f IN and then generates an error signal. According to that error signal the CP either increases or decreases the amount of charge to the LPF. This amount of charge either speeds up or slows down the VCO. The loop continues in this process until the phase difference between and is zero or constant—this is the locked mode. After the loop has attained a locked status, the loop still continues in the process but the output of each component is constant. The output signal has the same phase and/or frequency as .A divider can be used in the feedback path to synthesize a frequency different than that of the reference signal. The application I chose in designing the PLL was a frequency synthesizer. A frequency synthesizer generates a frequency that can have a different frequency from the original reference signal. iv LIST OF FIGURES Figure 1.Basic block