IBM PowerPC 403GA User’s Manual Ver 0.97, 24Mar95 IBM Confidential Second Edition (March 1995) This edition of IBM PowerPC 403GA User’s Manual applies to the IBM PPC403GA-JC 32-bit embedded controller, as well as to subsequent IBM PowerPC 400 embedded controllers until other- wise indicated in new versions or technical newsletters. The following paragraph does not apply to the United Kingdom or any country where such pro- visions are inconsistent with local law: INTERNATIONAL BUSINESS MACHINES CORPORA- TION PROVIDES THIS MANUAL “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Some states do not allow disclaimer of express or implied warranties in certain transactions; therefore, this statement may not apply to you. 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Ver 0.97, 24Mar95 IBM Confidential IBM Confidential Ver 0.97, 24Mar95 Contents 1Contents About This Book ............................................................................. xxv Overview ........................................................................................... 1-1 PPC403GA Overview .......................................................................................................... 1-1 PowerPC Architecture .......................................................................................................... 1-2 The PPC403GA as a PowerPC Implementation ............................................................. 1-2 PPC403GA Features ........................................................................................................... 1-3 RISC Core ....................................................................................................................... 1-4 Execution Unit (EXU) ................................................................................................. 1-4 Instruction Cache Unit (ICU) ...................................................................................... 1-5 Data Cache Unit (DCU) .............................................................................................. 1-6 Bus Interface Unit (BIU) .................................................................................................. 1-6 External Interfaces to DRAM, SRAM, ROM, and I/O ................................................. 1-6 RISC Core Interface ................................................................................................... 1-7 DMA Interface ............................................................................................................ 1-7 On-Chip Peripheral Bus Interface .............................................................................. 1-7 External Bus Master Interface .................................................................................... 1-8 DMA Controller ................................................................................................................ 1-8 Asynchronous Interrupt Controller .................................................................................. 1-9 Serial Port ....................................................................................................................... 1-9 Debug Port .................................................................................................................... 1-10 Data Types .................................................................................................................... 1-10 Register Set Summary .................................................................................................. 1-10 General Purpose Registers ...................................................................................... 1-10 Special Purpose Registers (SPR) ............................................................................ 1-11 Machine State Register ............................................................................................ 1-11 Condition Register .................................................................................................... 1-11 Device Control Registers .......................................................................................... 1-11 Addressing Modes ........................................................................................................ 1-11 Programming Model ........................................................................ 2-1 Chapter Overview ................................................................................................................ 2-1 Memory Organization and Addressing ................................................................................. 2-2 Double-Mapping .............................................................................................................. 2-2 Supported Memory .......................................................................................................... 2-3 Memory Map -- Cacheability Regions ............................................................................. 2-3 PPC403GA Register Set ...................................................................................................... 2-5 General Purpose Registers ............................................................................................. 2-5 Special Purpose Registers .............................................................................................. 2-5 Count Register (CTR) ................................................................................................. 2-6 Link Register (LR) ...................................................................................................... 2-7 Processor Version Register (PVR) ............................................................................. 2-8 Special Purpose Register General (SPRG0-SPRG3) ................................................ 2-8 Fixed Point Exception Register (XER) ....................................................................... 2-9 Ver 0.97, 24Mar95 IBM Confidential Contents v Condition Register (CR) ................................................................................................ 2-11 CR Fields after Compare Instructions ...................................................................... 2-12 The CR0 Field .......................................................................................................... 2-12 Machine State Register ................................................................................................ 2-13 Device Control Registers .............................................................................................. 2-14 Memory Mapped Input/Output