Processor Verification in Python Lavanya J Senior Project Officer | Shakti Lab | RISE Group | CSE Dept | IIT Madras DVClub Apr 2021 Agenda • Processor Adoption & Verification Trend • Shakti Introduction • Processor Verification Components • Python Packages for Verification • Why Python adoption ? 2 Trend: RISC-V Processors & Verification methodology RISC-V in nearly a quarter of the designs 124+ RISC-V Cores & SoCs 1000+ members in the RISC-V International (RI) consortium The 2020 study has included Python based verification methodology like CoCoTb for the first time Ref: Wilson Research Group and Mentor, A Siemens Business, 2020 Functional Verification Study 3 Shakti RISC-V Base Processors E-Class C-Class I-Class 3 Stage in-order 6 Stage in-order 12 Stage Out-of-order Low power-low compute With MMU support Performance oriented Running RTOs Running Linux & seL4 Linux & RTOs Targeting IoT & Robotics Targeting Control/Compute Targeting Compute/ Mobile platforms Applications platforms Coming Soon... Rise Creek RIMO Moushik 4 Shakti Processor Verification ● Based on open-source tools ● Simulation of Bluespec generated verilog design using Verilator ● Framework maintained commonly across E-Class, C-Class, I-Class cores maximizing reuse. ● Comprehensive suites of directed (risc-tests, riscv-compliance) and random assembly tests (Shakti’s AAPG) 5 Shakti Processor Verification ● Processor verification incorporates ISA level state checking at every instruction execution along with end of test memory check. 6 Processor Verification Components Random Assembly Spike Instruction Set Program Generator in Simulator - ISS Python (Shakti’s AAPG) Test Reference (C/C++) https://gitlab.com/shaktiproject/tools/aapg Generators Model Regression Scripting & RISC-V GNU Toolchain Continuous Toolchain for test Flow Integration (C/C++) compilation Automation (CI) Test Bench Coverage collection Verilator based code CoCoTb based RISC-V Processor coverage Python Testbench Verification CoCoTb-coverage Components for functional coverage definitions Why CoCoTb-Verilator over traditional methodology ? ● Quick framework ramp up with students and open source contributors alike ● Flexibility to setup the framework in remote workstations ● Ease of integration with external reference models ● Re-use of huge Python ecosystem libraries ● Does not compromise on verification quality ● Massive simulation parallelization is possible restricted only by the compute capability 8 CoCoTb-Verilator based verification ● Coroutine based Cosimulation Testbench (CoCoTb) provides standardized interfaces to talk to the RTL simulator ● CoCoTb library provided test bench components like drivers, monitors and scoreboard to implement a UVM based verification framework ● CoCoTb-Coverage package supports definitions for constraint random generation as well as functional coverage definition CoCoTb-Verilator based UVM framework 9 Conclusions and Future Work ● RISC-V processor verification in CoCoTb-Verilator leverages competitive, industry standard open source methodologies without compromising on the verification quality. ● Python based environment setup aids Shakti processors for rapid and cost effective design wins. ● Further steps are being explored to use Python at all verification abstraction levels. ● Shakti is collaborating with InCore Semiconductors-Tessolve for C-Class SoC development work. 10 Thank You! 11.