t Cortland Custom ICs rJ Preliminary l¡lotes rr¡/ritcr: Wayne lowry Apple User Education 030-1290-PN8 J Febnrary 14, 1986 o Copyright @ 1985 Appte Computer, Inc. All rights resert¡ed Changes Since Previous Draft These prcliminary notes arc the frnt drafr They are bascd primarily on the following ERS'S: . Mega / ERS 2.2, lune 25, 1985 . Fast Processor Interface (FPÐ ERS, Sepæmber 5, 1985 . Video Graphics Coneoller (VGC) ERS 2.0, October 8, 1985 . Slot Maker ERS, MaY 1, 1985 . Keygtu ERS 1.0, June 25, 1985 . Sound Glu ERS, June 21, 1985 . Front Desk Bus ERS Rev B, June 13, 1985 2/13t86 Preliminary Noæs ) Contents 6 Forword 1 Chapter 1: Cortland Custom ICs System Overview 7 lntroduction 7 Operadon 7 Sysæm Speed 7 Shadowing I The Video Graphics Controller I Memory Allocation 11 Chapter 2: Fast Processor Interface ì 11 lntroduction 11 Operæion Controi 11 Sanda¡d Soft Swirches 12 Memory Allocation 13 Ih" lt"ç Register = cl 13 Shadowing -..1 t3 The Shadow Register = cP 14 Shadowed lvfemory lvlap 15 The CYA Regisær = cþ 16 High Speed Operation 16 Disk Motor-ûr Deæctors L7 RAlvf Control t7 Addrcss Multiplexing t7 RAlvf Refrcshing t7 Refrcsh Requests and Arbitration t7 CASiRAS Refrcsh t7 ROtYf Control 18 Bar¡ks SFB and SFE-FF 18 Exænded Memory Card Slot l8 Exte¡ded R.A,ñf i8 Exænded RAt\4 Mapping 19 MSizc l9 Ghosting 20 Exænded ROM 2L I/O Processing 2t The Slot ROM Register 22 Mega II Interface 1'.) M-Saæ Counter 11 Synchronization 22 Mega tr Cycles 23 $Eo-$Er )a Mega II Bank Bit 73 D}IA 24 Timing Control 24 F-Staæ Machine 24 P-Staæ Machine J Preliminary Noæs 2t13t86 24 Inærfacing the Cortland Sysæm 24 Frogrammed VO Ca¡ds 25 DlvfA Cads 27 Chapter 3: Mega tr Z7 Introduction 28 Mega tr Select Functions 28 Support of Inærnal Devices 28 RAN4 Refresh 29 Mouse/Game VO Operations 29 Intemtpts 30 Game VO 30 lnæmrpt ROM 30 Video 30 Composia G\ffSC) 31 RGB 31 Text 33 Graphics 34 Memory Transiation 34 State Regisær 34 Seiect Signai 35 Video Regsæn 37 Chapter 4: Video Graphics Controller 31 lntroduction 38 The VGC Suppora Apple II Video Modes 38 Text Background Register 38 Border Color Regisær 38 Mono/Coior Regisær 39 New Video Modes 40 The Display Buffer 40 Poinær Bytes 4I Coior Palenes 43 Pixels U Polygon FiIl Mode 44 Clock Chip Interface 45 VGC lntemrpt Regisæn 46 VGC Disk Register 46 VGC Test Modes 47 Chapter 5: Slot Maker 47 Generai Descripuon 49 Chapter 6: Key Glu 49 lntroduction 49 Key Glu Read-Only Status Regisær 49 Sysrem St¿tus Regisær 49 Status Flags 51 Chapter 7: Sound GIU 51 Introduction 5i Vlriæ Operation 5i Read Operauon 7t13t86 heliminary Noæs 4 Bus 55 Chapter E: Front Desk )J lntroduction )J Physicai L:yet 53 Modulation 53 Normal Modulæion 53 High Spe€dModulation 53 Sienals- 54 A¡ændon utd SYnc 54 Reset 54 Sen¡ice Request 54 Transactions 54 Data Link )J F *t Desk Bus PeriPherals )) Registøs ') )) Commands 56 Talk )o Lisæn 56 SendReset 56 Flush )o Co[ision Detcction io Er¡or Conditions 51 Ñitwort LaYer 6DB TYPes) >t Normal Devices 57 Exændcd Address Devices 58 Register 3 -S-åiJntqotst Enabling 59 a¡rd High SP€ed IVOZ Machine 61 ChaPter 9: Integrated 6i lnroduction 61 Conaoi Registers 61 State Regisær 62 t'to¿e Rãgistcr Cw¡tç-9niJ I 63 Stan¡s Re-gister fr'ead-OnlY) . ) I 63 flã¿ttt¡å Regisær ßead-OnlY 63 Data Register Generator ROM ô5 Appendix A: Mega II Character Timing 67 APPendix B: Cortland InPut/OutPut 73 APPendix C: Signal DescriPtions i¡ 2tL3t86 D-aliçri¡qn¡ NOtgS 5 Forword These preliminary notes for thc Conla¡d CuspmlCs manual do not consdn¡te a book They aie mercly ä co[ection of notes and fragmenary information and ar€ not guaranteed to be either compÍetc or correçL Their only reason to be is their availability now, so far in advance of thé product they describe. Afær the dcveloper seeding, the i¡rformation in these notcs will be incorporated into the Conland CusnmlCs manuat. Thæ book wiI be the included in a¡rother manual (currcnt plan) in the suiæ of æchnical manuais for the Conland. fl Preliminary Noæs 6 2/13i86 Chapter L Cortland Custom ICs System Overview Introduction The Cortland system is divided into cwo sepÍ¡rate subsysæms. Onq subsystem consists of t¡i trt"g. II, liSK of standard Apple il-rnemory, video generation logig, inæ¡nai and ;it -ri UO siots (right of dotæd line, Figurc i). Tt¡is.subsysæm is rcf"¡*$ to as the ,\ Mega II side of the systern The other subsys-tem consists of the 65CE IÓ mrcroprocessor' t¡.F.st Processor Inicrface (FPÐ IC, up to +M byæs of fast dynamic RA-tvf, .6aK b-yt99 of- nóvq -¿ ud¿ition'¡ internaì Vo registèn. This iubsysæm is referred to as the FPI side of the system (lower-left of doned üne, Figurc 1). Operation The F?I IC is thc processor and memory controller fgr the fastpa¡ of the Cortland system- It controls the sysiem speed, manages and refreshes the expanded system memory. The Mega tr IC is the integration and enhancement of several.Appte II chips:.an-APPl9 þn ;;Hp.-ihus,Ãppte II fealtures arc accessible within the Cortland system a¡rd all Apple II softwa¡e is compatible. System Speed ln normal operation, the Coniand system runs the FPI side.of the system at2-8 MI{z and m ftfrgi ll'side at í.OZq MHz. Îús ailows faster processing without disturbing.the it-¿-ã I MHz VO a¡rd video dming that is rcquircd for compatibility with exisdng perpirerA units. To run the system õpdmalty, the FPI side of the system provides a iftaàont"g fean¡re that allowi accesito I/O a¡rd the Mega II's video buffen. Shadowing The Co¡tland sysæm uses the shadowing method to process the video displays while ¿ìrca. Wriæ-o-perago¡s performed.using running progra;$ in the fast RAlvf $1are . the fast RAM a¡rd the MçSa g thu¡ thg try sþdoytin_gt ritøoõii,g ú¡æ in both ry{&q . iiãory ñad operations, however, are performedõnly from the fast RA-lvf" Fast RAlvf is used belause thè System must slow down to access the slower Mega tr RAlYf. Preliminary Noæs 7 2tr4t86 The Video Graphics Controller The Video Graphics Controller CVGC) IC suppors.and enha¡ces eústing Appie.tr video, iotof".rt withihe Macintosh clock chip, proïides inæm¡pt processing-fgr thrce intemrpt ró*6, implements video modes, anaþoviaes test modet for chip3nd board-level ô-tting.'firå vCC provides these feanrès in concert with the Mega tr (upper-right middle of Figure l). brl st ¡ I I I t a t tæI L L L ! L L L o5 D' o o o o o o o ¡afi t¡i ? IC ! 1 ? I I 1 f ra I 2 t a ú a 1 t¡traal c¡r vo ¡t¡a il ttt G I g g ú ú C I - E r x 5 E o ¡¡o^ , Ê o Oæ 31'i' IAI'T í:t c¡.ær ¡aro o¡1, E g 5. 3 g EÞ tlt ¡ ¡ - - It¡a^ Éltro I aælra ñ g/ t, ttÈ :l I __l ¡^ I ao- I rta¡ E ;i Oar t¡ãr ri¡ trg¡ I ¡o,tÎ ll- @ lrÉ¡fE¡ tllßr ll¡lt ta Jf¡ Figure t. Cortland Block Diagram Memory Allocation A minimum Conland system includes 256K bytes of RAM and.64K bytes of ROM' The co¡responds to, the currcnt Apple.II^family it4;!; Iriãe includes t2ar uyæ! gf RAlvf thai , Main and Aux memory bar¡kí. This RAlvf is used foiæxt_an{ Sraphics display buffen a¡d io i,orl6n^in syste-ioftwa¡e in rcserved a¡eas. The FPI side of the sysæm inciudes a ilúñ oirzÉr uiær ãrn¡r"r, 6+K byær of RoM, and is expandable to a maximum of 4128K byæs of RAM (see Figure 2). Preliminary Noæs I 2tr4t86 ,l $0 u Main board fast128K RAM and l/O , 4&f Ogiu*rÀ ø*& v"¡in boart þ" f '\ay $1 W 902-7F 8M bytes Memory .*p?ffi,$ñfktr. i?,:,r,"^,,,)1* ; - unused $80-DF 6M bytes Reserved currentlY $E0 Main board slow Mega ll 128K RAM, and l/O space $El currently unused $E2.EF 896K bYtes Reserved' exparsion card, RoM area $FO.FD 896K bytes Memory LL*j äik* *, ROM area $FE+F 641128K bytes Main board fast -*----' Figure 2. Bank MemorY MaP j |r ..l r' t?- 3¿ [<or orlcLtr"n +-r ^t0tr l- Ë. 4f0 !l P ib. íi ', a.^ ) dL 19'';dJ¿) \o h- d'ry^'rt )>?.Sl l¡Âxl ùp, (* V ø(hnne,r,n ca.À \A b 4¡ "-fl^ J 2/r1t86 Preliminary Notes 9 2t11t86 PreiimrnarY Noæs 10 Chapter 2 Fast Processor Interface Introduction The Fast Processor Inærface IC (FPÐ is the processor and mcmory controiler for the fast part of the Cortland systern It controls thg sV¡ær-n sPce,+ manages and refrcshes the VO and the ã*p-a.a system rnemory,-This and provides the slødowtlS that allows access to Mèga II's video buffers. süb-system is referrcd to as the F?I side of the system (see Figures I and 3). Dnring normal operation, the_Co4land system runs the FPI sidc of the lysæm at2-8 MHz -d rË Mega n ii¿e at 1 MHz. This ailõw* t'astef processing without disnrrbing.