Intel Cyclone 10 LP Device Design Guidelines Subscribe AN-800 | 2019.03.28 Send Feedback Latest document on the web: PDF | HTML Contents Contents Intel® Cyclone® 10 LP Device Design Guidelines.................................................................4 Design Flow................................................................................................................ 4 System Specification.................................................................................................... 5 Design Specifications...........................................................................................6 IP Selection........................................................................................................6 Platform Designer............................................................................................... 7 Device Selection.......................................................................................................... 7 Device Variant.................................................................................................... 8 PLLs and Clock Routing........................................................................................8 Logic, Memory, and Multiplier Density.................................................................... 8 I/O Pin Count, LVDS Channels, and Package Offering............................................... 9 Speed Grade...................................................................................................... 9 Vertical Device Migration.................................................................................... 10 Early System and Board Planning................................................................................. 10 Early Power Estimation...................................................................................... 10 Planning for Device Configuration........................................................................ 12 Planning for On-chip Debugging.......................................................................... 14 Pin Connection Considerations for Board Design............................................................. 16 Device Power-Up...............................................................................................16 Power Pin Connections and Power Supplies........................................................... 17 Configuration Pin Connections.............................................................................18 Board-related Intel Quartus Prime Settings...........................................................21 Signal Integrity Considerations........................................................................... 22 Board-level Simulation and Advanced I/O Timing Analysis...................................... 23 I/O and Clock Planning................................................................................................23 Making FPGA Pin Assignments.............................................................................24 Early Pin Planning and I/O Assignment Analysis.....................................................24 I/O Features and Pin Connections........................................................................25 Clock and PLL Selection..................................................................................... 28 PLL Feature Guidelines.......................................................................................29 Clock Control Features....................................................................................... 29 I/O Simultaneous Switching Noise....................................................................... 30 Design Entry..............................................................................................................30 Design Recommendations.................................................................................. 30 Using IP Cores.................................................................................................. 31 Recommended HDL Coding Styles....................................................................... 31 Register Power-up Levels and Control Signals....................................................... 31 Design Implementation, Analysis, Optimization, and Verification....................................... 33 Selecting a Synthesis Tool.................................................................................. 33 Device Resource Utilization Reports..................................................................... 34 Intel Quartus Prime Messages.............................................................................34 Timing Constraints and Analysis.......................................................................... 34 Area and Timing Optimization............................................................................. 36 Preserving Performance and Reducing Compilation Time.........................................36 Simulation....................................................................................................... 37 Power Analysis..................................................................................................37 Power Optimization........................................................................................... 38 Intel Cyclone 10 LP Device Design Guidelines Send Feedback 2 Contents Document Revision History for Intel Cyclone 10 LP Device Design Guidelines......................40 Send Feedback Intel Cyclone 10 LP Device Design Guidelines 3 AN-800 | 2019.03.28 Send Feedback Intel® Cyclone® 10 LP Device Design Guidelines It is important to follow Intel design guidelines and recommendations throughout the design process for Intel® Cyclone® 10 LP designs. The design guidelines also assist you with planning the FPGA and system early in the design process, which is crucial to successfully meet design requirements. Note: For more information about Intel Cyclone 10 LP devices and features, refer to the Intel Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook. The material references the Intel Cyclone 10 LP device architecture as well as aspects of the Intel Quartus® Prime software and third-party tools that you might use in your design. These guidelines can improve productivity and avoid common design pitfalls. Related Information Cyclone 10 LP Device Handbook Provides more information about the Cyclone 10 LP devices. Design Flow Table 1. Summary of the Design Flow Stage and Guideline Topics Stages of the Design Flow Description System Specification Planning design specifications, IP selection Device Selection Device information, determining device variant and density, package offerings, migration, speed grade Early System and Board Planning Early power estimation, thermal management option, planning for configuration scheme, planning for on-chip debugging Pin Connection Considerations for Power-up, power pins, PLL connections, decoupling capacitors, configuration Board Design pins, signal integrity, board-level verification I/O and Clock Planning Pin assignments, early pin planning, I/O features and connections, memory interfaces, clock and PLL selection, simultaneous switching noise (SSN) Design Entry Coding styles and design recommendations, Platform Designer (Standard), planning for hierarchical or team-based design Design Implementation, Analysis, Synthesis tool, device utilization, messages, timing constraints and analysis, area Optimization, and Verification and timing optimization, compilation time, verification, power analysis and optimization Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015 at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. Intel® Cyclone® 10 LP Device Design Guidelines AN-800 | 2019.03.28 Figure 1. Intel Cyclone 10 LP Device Design Flow Start System Specification Design Specification IP Selection Device Selection Considerations for HDL and Early HDL Development Early System and Board Planning Board Development Start Platform Designer/ Configuration Power HDL Design with Avalon Bus Clock and PLL Debugging Capability Thermal Selection Nios II Signal Integrity Decoupling I/O Features and Dynamic Reconfiguration Layout Pin Connections Design Implementation Memory Interfaces Timing Constraints and Analysis Simulation Design Verification End System Specification In systems that contain an Intel Cyclone 10 LP device, the FPGA typically plays a large role in the overall system and affects the rest of the system design. It is important to start the design process by creating detailed design specifications for the system and the FPGA, and determining the FPGA input and output interfaces to the rest of the system. Send Feedback