Floating-Point Operator v7.1 LogiCORE IP Product Guide Vivado Design Suite PG060 December 16, 2020 Table of Contents IP Facts Chapter 1: Overview Navigating Content by Design Process . 2 Core Overview . 2 Unsupported Features. 2 Licensing and Ordering . 3 Chapter 2: Product Specification Standards . 4 Performance. 6 Resource Utilization. 7 Port Descriptions . 8 Chapter 3: Designing with the Core General Design Guidelines . 14 Accumulator Design Guidelines . 17 Clocking. 19 Resets . 20 Protocol Description . 20 Chapter 4: Design Flow Steps Customizing and Generating the Core . 28 Constraining the Core . 38 Simulation . 39 Synthesis and Implementation . 39 Chapter 5: C Model Features . 40 Overview . 40 Unpacking and Model Contents . 41 Installation . 42 C Model Interface. 42 Compiling . 62 Floating-Point Operator v7.1 Send Feedback 2 PG060 December 16, 2020 www.xilinx.com Linking. 63 Dependent Libraries . 64 Example . 65 Chapter 6: Test Bench Demonstration Test Bench . 67 Appendix A: Upgrading Migrating to the Vivado Design Suite. 69 Upgrading in the Vivado Design Suite . 69 Appendix B: Debugging Finding Help on Xilinx.com . 73 Debug Tools . 74 Simulation Debug. 75 AXI4-Stream Interface Debug . 75 Appendix C: Additional Resources and Legal Notices Xilinx Resources . 76 Documentation Navigator and Design Hubs . 76 References . 76 Revision History . 77 Please Read: Important Legal Notices . 78 Floating-Point Operator v7.1 Send Feedback 3 PG060 December 16, 2020 www.xilinx.com IP Facts • Fully synchronous design using a single Introduction clock The Xilinx® Floating-Point Operator core LogiCORE IP Facts Table provides you with the means to perform floating-point arithmetic on an FPGA. The core Core Specifics can be customized for operation, wordlength, UltraScale+™ UltraScale™ latency and interface. Supported Device Versal™ ACAP Family(1) Zynq®-7000 SoC 7 Series Supported User AXI4-Stream Features Interfaces Performance and Resource Utilization web Resources • Supported operators: page ° Multiply Provided with Core ° Add/subtract Design Files Encrypted RTL ° Accumulator Example Design Not Provided ° Fused multiply-add Test Bench VHDL ° Divide Constraints File Not Provided ° Square-root Simulation Model Encrypted VHDL, C Model Comparison Supported ° N/A S/W Driver ° Reciprocal Tested Design Flows(2) ° Reciprocal square root Vivado® Design Suite ° Absolute value Design Entry System Generator for DSP Natural logarithm ° For supported simulators, see the Simulation ° Exponential Xilinx Design Tools: Release Notes Guide. ° Conversion from floating-point to Synthesis Vivado Synthesis fixed-point Support Conversion from fixed-point to ° Release Notes and AR: 54504 floating-point Known Issues Conversion between floating-point All Vivado IP ° Master Vivado IP Change Logs: 72775 types Change Logs Xilinx Support web page ° Unfused multiply-add ° Unfused multiply-accumulator Notes: Accumulator primitive 1. For a complete listing of supported devices, see the Vivado IP ° catalog. •Compliance with IEEE-754 Standard [Ref 1] 2. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide. (with only minor documented deviations) • Parameterized fraction and exponent wordlengths for most operators • Optimizations for speed and latency Floating-Point Operator v7.1 Send Feedback 1 PG060 December 16, 2020 www.xilinx.com Product Specification Chapter 1 Overview Navigating Content by Design Process Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. This document covers the following design processes: • Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardware platform, creating PL kernels, subsystem functional simulation, and evaluating the Vivado timing, resource and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include: ° Port Descriptions ° Clocking ° Resets ° Customizing and Generating the Core ° C Model Core Overview The Xilinx Floating-Point Operator core allows a range of floating-point arithmetic operations to be performed on FPGA. The operation is specified when the core is generated, and each operation variant has a common interface. This interface is shown in Figure 2-1. Unsupported Features See Standards. Floating-Point Operator v7.1 Send Feedback 2 PG060 December 16, 2020 www.xilinx.com Chapter 1: Overview Licensing and Ordering This Xilinx LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado® Design Suite under the terms of the Xilinx End User License. Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. For information about pricing and availability of other Xilinx LogiCORE IP modules and tools, contact your local Xilinx sales representative. Floating-Point Operator v7.1 Send Feedback 3 PG060 December 16, 2020 www.xilinx.com Chapter 2 Product Specification Standards IEEE-754 Support The Xilinx® Floating-Point Operator core complies with much of the IEEE-754 Standard [Ref 1]. The deviations generally provide a better trade-off of resources against functionality. Specifically, the core deviates in the following ways: • Non-Standard Wordlengths • Denormalized Numbers • Rounding Modes • Signaling and Quiet NaNs Non-Standard Wordlengths The Xilinx Floating-Point Operator core supports a different range of fraction and exponent wordlength than defined in the IEEE-754 Standard. Basic Formats: • binary16 (Half Precision Format) – Uses 16 bits, with an 11-bit fraction and 5-bit exponent. • binary32 (Single Precision Format) – Uses 32 bits, with a 24-bit fraction and 8-bit exponent. • binary64 (Double Precision Format) – Uses 64 bits, with a 53-bit fraction and 11-bit exponent. • binary128 (Quadruple Format) – not supported Extendable Precision Formats (not available on all operators): • Uses up to 80 bits. • Exponent width of 4 to 16 bits. Floating-Point Operator v7.1 Send Feedback 4 PG060 December 16, 2020 www.xilinx.com Chapter 2: Product Specification • Fraction width of 4 to 64 bits Note: Limitations apply based on exponent width. See the Vivado® Integrated Design Environment for actual ranges. Denormalized Numbers The exponent limits the size of numbers that can be represented. It is possible to extend the range for small numbers using the minimum exponent value (0) and allowing the fraction to become denormalized. That is, the hidden bit b0 becomes zero such that … < b0.b1b2 bp – 1 1 . Now the value is given by: w – 1 –2 e – 2 s v1= ()– 2 0.b b …b 1 2 wf – 1 These denormalized numbers are extremely small. For example, with single precision the –126 value is bounded v < 2 . As such, in most practical calculation they do not contribute to the end result. Furthermore, as the denormalized value becomes smaller, it is represented with fewer bits and the relative rounding error introduced by each operation is increased. The Xilinx Floating-Point Operator core does not support denormalized numbers for most operators. In FPGAs, the dynamic range can be increased using fewer resources by increasing the size of the exponent (and a 1-bit increase for single precision increases the 256 range by 2 ). If necessary, the overall wordlength of the format can be maintained by an associated decrease in the wordlength of the fraction. To provide robustness, the core treats denormalized operands as zero with a sign taken from the denormalized number. Results that would have been denormalized are set to an appropriately signed zero. The exception to the above rules is the absolute value operator, which propagates denormalized operands to the output. The support for denormalized numbers cannot be switched off on some processors. Therefore, there might be very small differences between values generated by the Floating-Point Operator core and a program running on a conventional processor when numbers are very small. If such differences must be avoided, the arithmetic model on the conventional processor should include a simple check for denormalized numbers. This check should set the.