A DUAL-LOOP FREQUENCY SYNTHESIZER by LALITH KARSANI, B.E. A THESIS IN ELECTRICAL ENGINEERING Submitted to the Graduate Faculty of Texas Tech University in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING Approved Kwong S. Chao Chairperson of the Committee Sunanda Mitra Accepted John Borrelli Dean of the Graduate School December, 2006 ACKNOWLEDGEMENTS It has been a great privilege to be a graduate student in the Electrical and Computer Engineering department at the Texas Tech University and work closely with my advisor Prof. Dr. Kwong S. Chao. His keen insight into system and integrated circuit design is the key factor in the success of this research. I would also like to thank Prof. Dr. Sunanda Mitra, for her willingness to serve in my committee. I greatly appreciate my colleagues in Dr. Chao’s group for the numerous technical discussions. I would like to thank Chintan Trehan who has worked closely with me in the past two years. He is a person who would never run out of ideas. I thank my friends for all the encouragement and support. The financial assistance in the form of scholarship from Electrical and Computer Engineering department is appreciated. I would also like to acknowledge and appreciate the financial assistance provided by Lucia S. Barbato, Senior Research Associate, Center for Geospatial Technology. I am grateful to my parents for their love and support in my whole life. Their confidence in me and their high expectation of me are the driving forces for completion of this work. ii TABLE OF CONTENTS ACKNOWLEDGEMENTS ii ABSTRACT v LIST OF FIGURES vi CHAPTERS I. INTRODUCTION 1 1.1 Motivation 1 1.2 Organization of the Thesis 5 1.3 Terms used in PLL Literature 5 1.4 Types of PLL 7 1.4.1 ADPLL 8 II. BASIC BUILDING BLOCKS 9 2.1 Phase detector 10 2.2 Voltage controlled oscillator 11 2.3 Loop filter 13 2.4 Charge pump 13 2.5 Bandwidth of PLL 15 III. PROPOSED ARCHITECTURE 18 3.1 Dual feedback frequency synthesizer 18 3.1.1 Operation of FVC loop 21 3.1.2 Effect of FVC on the synthesizer system 22 3.2 Loop parameter design 24 IV. CIRCUIT LEVEL DESIGN OF THE PROPOSED ARCHITECTURE 27 4.1 Phase frequency detector 27 4.2 Charge pump 32 4.2.1 Buffer Stages 34 4.2.2 Current Sources 35 4.3 Voltage controlled oscillator 35 iii 4.4 Loop filter 41 4.5 Divider 43 4.6 Frequency-to-Voltage Converter 46 4.6.1 Pulse-to-Digital Converter 47 4.6.2 Digital-to-Analog Converter 51 4.7 Dual-loop frequency synthesizer 58 V. SIMULATIONS AND RESULTS 61 VI. CONCLUSIONS AND FUTURE WORK 70 VII. REFERENCES 71 iv ABSTRACT A dual-loop frequency synthesizer is proposed to reduce the phase noise introduced by the Voltage Controlled Oscillator (VCO) which is the main source of noise in a traditional PLL-based frequency synthesizer. The focus of this thesis is on the analysis and simulation of the proposed dual-loop frequency synthesizer architecture and comparison of results with that of the standard frequency synthesizer. Instead of the traditional PLL-based frequency synthesizer with a single feedback loop from the VCO output through a divider back to the phase detector, an additional feedback path from the VCO output through a Frequency-to-Voltage Converter (FVC) to the input of the loop filter is introduced. Results show considerable improvement in the phase noise performance and the lock time. The improved performance can be attributed to noise suppression in the loop for reasons similar to a sigma-delta modulator. Due to this improved noise performance, a dual-loop frequency synthesizer is suitable for applications which require high phase noise suppression. v LIST OF FIGURES 1.1 PLL-based frequency synthesizer 2 1.2 First-order sigma-delta modulator 3 1.3 Second-order sigma-delta modulator 3 1.4 Equivalent of Second-order sigma-delta modulator 4 1.5 Dual-loop frequency synthesizer 4 1.6 Scope of static and dynamic limits of stability of a PLL 7 1.7 All digital phase locked loop 8 2.1 A basic phase locked loop synthesizer 9 2.2 Phase detector characteristic 10 2.3 Signal flow model of phase detector 11 2.4 VCO characteristic 12 2.5 Signal flow model of VCO 13 2.6 Charge pump 14 2.7 Average current vs. phase error plot 15 2.8 Linear model of a PLL 16 3.1 Desired frequency spectrum of synthesizer 18 3.2 Measured frequency spectrum of synthesizer 19 3.3 Sources of noise in synthesizer 20 3.4 Block diagram of FVC 22 3.5 Dual-loop synthesizer model 22 3.6 Noise transfer function of dual-loop synthesizer 23 3.7 Magnitude plot of FVC noise 24 3.8 Loop filter response curve 25 4.1 Implementation of phase frequency detector 27 4.2 Positive edge-triggered D-flip-flop with reset 28 4.3 Two-input NOR gate 29 4.4 State diagram of PFD 30 vi 4.5 Dead zone in PFD 31 4.6 Two-input AND gate 32 4.7 Charge pump implementation 33 4.8 Inverter schematic 34 4.9 VCO differential cell 36 4.10 Voltage controlled oscillator schematic 37 4.11 VCO transfer characteristic curve with out self bias 38 4.12 VCO transfer characteristic curve with self bias 39 4.13 Power spectral density of VCO 40 4.14 Periodic phase noise response 41 4.15 Second-order passive lead-lag filter 42 4.16 Magnitude and phase response of loop filter 43 4.17 T-flip-flop and its input-output waveforms 44 4.18 Divide-by-32 circuit 45 4.19 Waveforms of divide-by-32 circuit 45 4.20 Frequency-to-Voltage Converter 46 4.21 Characteristic curve of FVC 47 4.22 Pulse generating circuit 48 4.23 Output of pulse generating circuit 49 4.24 4-bit counter 50 4.25 Pulse-to-Digital Converter 51 4.26 Digital-to-Analog Converter 52 4.27 Two-stage op-amp 53 4.28 AC response of op-amp 55 4.29 Step response of op-amp 56 4.30 Characteristic curve of DAC 57 4.31 Complimentary CMOS switch 58 4.32 Implemented PLL-based frequency synthesizer 59 4.33 Implemented dual-loop frequency synthesizer 60 vii 5.1 VCO control voltage for PLL-based frequency synthesizer 61 5.2 VCO control voltage for dual-loop frequency synthesizer 62 5.3 Ripple in control voltage after lock for PLL-based frequency synthesizer 63 5.4 Ripple in control voltage after lock for dual-loop frequency synthesizer 64 5.5 Lock-in process of reference and VCO frequencies 65 5.6 PSD of VCO output for PLL-based frequency synthesizer 66 5.7 Zoom-in of Figure 5.6 67 5.8 PSD of VCO output for dual-loop frequency synthesizer 68 5.9 Zoom-in of Figure 5.8 69 viii CHAPTER 1 INTRODUCTION 1.1 Motivation Phase Locked Loops (PLL) find wide applications in areas such as communications, wireless systems, digital circuits, and disk drive electronics. While the concept of phase locking has been in use for more than half a century, monolithic implementation has become possible only around 1965. A few years later the first digital PLLs became available. Recent advances in integrated circuit design techniques have led to an increased use of the PLL as it has become more economical and reliable. A PLL is a circuit synchronizing an output signal with a reference or input signal in frequency as well as in phase. It can be considered as a negative feedback control system. The basic building blocks of PLL are Phase Detector (PD), Loop Filter (LF) and Voltage Controlled Oscillator (VCO) The PD is a circuit capable of delivering an output signal that is proportional to the phase difference between its input signal and the feedback signal. This output signal of PD consists of a dc component and a superimposed ac component. The latter is undesired, hence it is canceled by the loop filter. In most cases a first-order, low-pass filter is used. This dc control voltage from the loop filter controls the VCO output frequency. Due to the negative feedback, the loop will make sure the output signal is in phase with the reference signal. When this happens the phase error between the input and output frequencies is zero and PLL is said to be in lock. As long as the initial difference between the input signal and the VCO is not too big, the PLL eventually locks onto the input signal. This period of frequency acquisition, is referred to as pull-in time, which depends on the bandwidth of the PLL. The bandwidth of a PLL depends on the characteristics of the phase detector, voltage controlled oscillator and on the loop filter. The above described architecture with a divider in the feedback is widely used as a frequency synthesizer and is shown in Figure 1.1. PLL can be thought of as a 1 synthesizer with output frequency equal to reference frequency. Most of the research in this field is done on optimizing individual building blocks to get better performance. The most important component with respect to noise in a PLL is the oscillator. Digital PLL (DPLL) is more suitable for implementation on an integrated circuit than the linear PLL. Digital versions of VCO are called Digital Controlled Oscillator (DCO). But DCO is more prone to phase noise than VCO.