UNIVERSITY OF CALIFORNIA Los Angeles Power Optimization of Sum-of-Products Design for Signal Processing Applications A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science by Seok Won Heo 2014 © Copyright by Seok Won Heo 2014 ABSTRACT OF THE DISSERTATION Power Optimization of Sum-of-Products Design for Signal Processing Applications by Seok Won Heo Doctor of Philosophy in Computer Science University of California, Los Angeles, 2014 Professor Miloš D. Ercegovac, Chair Power consumption is a critical aspect in today’s mobile environment, while higher performance remains a major design goal. In recent mobile devices, the signal processing applications are power-consuming due to the frequent use of arithmetic computations; hence they have a large impact on the overall power dissipation. Specifically, a sum-of-products is a frequently used arithmetic operation in signal processing applications. Conventional designs use separate multipliers and adders in implementing sum-of-products. In this dissertation, we focus on developing a low-power arithmetic unit to perform a sum-of-products operation. The objective of this research is to investigate the algorithmic and architectural approaches for low-power and high-performance design of a sum-of-products with multi-functional computing ability, SIMD and approximate operations, and to demonstrate its capabilities in representative signal processing applications. The key distinguishing features of our approach is to develop a sum-of-products systematically from two aspects: internal efforts considering the arithmetic architecture and external efforts considering input data characteristics. We evaluate the power, delay and area of our solutions, and then compare our designs with similar ii arithmetic schemes. The benchmark evaluations are used to identify benefits and limitations of our solutions in signal processing applications. iii The dissertation of Seok Won Heo is approved. Jingsheng Jason Cong Yuval Tamir Dejan Marković Miloš D. Ercegovac, Committee Chair University of California, Los Angeles 2014 iv To my parents, brother and wife v Table of Contents Chapter 1 Introduction ................................................................................................... - 1 - 1.1 The Main Research Problem ......................................................................... - 1 - 1.2 Motivation ..................................................................................................... - 5 - 1.3 Power Optimization ...................................................................................... - 7 - 1.4 Low-Power Multiplier Design .................................................................... - 12 - 1.5 Research Approach ..................................................................................... - 16 - 1.6 Organization of Dissertation ....................................................................... - 17 - Chapter 2 Power Optimization of an Array Multiplier................................................ - 20 - 2.1 Introduction ................................................................................................. - 21 - 2.2 Related Work .............................................................................................. - 23 - 2.3 The Left-to-Right Array Multiplier ............................................................ - 24 - 2.4 Structure Optimization ................................................................................ - 25 - 2.4.1 Partial Product Generation with Radix-4 Recoding .................................... - 28 - 2.4.2 The [4:2] Adder for PP Reduction .............................................................. - 29 - 2.4.3 The Split Array: Even/Odd and Upper/Lower ............................................ - 32 - 2.4.4 Voltage Islands............................................................................................ - 40 - 2.5 Experimental Evaluation ............................................................................. - 42 - 2.5.1 Results for Split Array Multipliers ............................................................. - 42 - 2.5.2 Results for Voltage Islands Technique ....................................................... - 44 - 2.6 Summary ..................................................................................................... - 48 - Chapter 3 Power and Delay Optimization of the Carry-Propagate Adder .................. - 50 - 3.1 Introduction ................................................................................................. - 50 - vi 3.2 Problem and Related Work ......................................................................... - 51 - 3.2.1 Problem ....................................................................................................... - 51 - 3.2.2 Related Work .............................................................................................. - 51 - 3.3 Baseline Design .......................................................................................... - 57 - 3.3.1 Preliminaries ............................................................................................... - 57 - 3.3.2 Basic Schemes and Architecture of the CSELA ......................................... - 61 - 3.4 The Proposed Design .................................................................................. - 65 - 3.4.1 Modified Schemes and Architecture of the CSELA ................................... - 65 - 3.4.2 Optimal Group Distribution ........................................................................ - 74 - 3.4.3 The Structure Optimization......................................................................... - 74 - 3.5 Experimental Evaluation ............................................................................. - 83 - 3.5.1 Results for Split Array Multipliers ............................................................. - 83 - 3.6 Summary ..................................................................................................... - 86 - Chapter 4 Low-Power Sum-of-Products Unit for Signal Processing Applications ..... - 87 - 4.1 Introduction ................................................................................................. - 87 - 4.2 Sum-of-Products Design ............................................................................. - 89 - 4.2.1 The Proposed Design .................................................................................. - 89 - 4.3 Experimental Results .................................................................................. - 92 - 4.3.1 ARM Multiplier Results ............................................................................. - 94 - 4.3.2 The Design Characteristics of the Proposed Sum-of-Products Units ....... - 103 - 4.4 Summary ................................................................................................... - 109 - Chapter 5 Multi-functional Arithmetic Unit based on Sum-of-Products .................. - 111 - 5.1 Introduction ............................................................................................... - 111 - 5.2 MAU-SoP Structure .................................................................................. - 112 - 5.2.1 The Opcode Decoder ................................................................................ - 113 - vii 5.2.2 The Heterogeneous Sum-of-products Unit ............................................... - 115 - 5.3 Arithmetic Operations ............................................................................... - 116 - 5.3.1 Sum-of-products ....................................................................................... - 116 - 5.3.2 Multiplication ............................................................................................ - 116 - 5.3.3 Multiply-add ............................................................................................. - 118 - 5.3.4 Sum-of-squares ......................................................................................... - 119 - 5.3.5 Square ....................................................................................................... - 120 - 5.3.6 Add-multiply ............................................................................................. - 127 - 5.3.7 Overall Execution ..................................................................................... - 129 - 5.4 Experimental Evaluation ........................................................................... - 133 - 5.5 Summary ................................................................................................... - 137 - Chapter 6 SIMD and Approximate Arithmetic Unit based on Sum-of-Products ...... - 138 - 6.1 Introduction ............................................................................................... - 138 - 6.2 Related Work ............................................................................................ - 140 - 6.3 The Proposed Arithmetic Unit .................................................................. - 142 - 6.3.1 The SAAU-SoP Structure ......................................................................... - 142 - 6.3.2 The Proposed Operations .......................................................................... - 144 - 6.4 Basic Components .................................................................................... - 155 - 6.4.1 Dynamic Range Detector and Main Controller .......................................