MIPS® Architecture For Programmers Volume I-B: Introduction to the microMIPS32™ Architecture Document Number: MD00741 Revision 6.00 November 8, 2015 Public. This publication contains proprietary information which is subject to change without notice and is supplied ‘as is’, without any warranty of any kind. MIPS® Architecture For Programmers Volume I-B: Introduction to the microMIPS32™ Architecture, Revision 6.00 Contents Chapter 1: About This Book ................................................................................................................ 12 1.1: Typographical Conventions ....................................................................................................................... 13 1.1.1: Italic Text.......................................................................................................................................... 13 1.1.2: Bold Text.......................................................................................................................................... 13 1.1.3: Courier Text ..................................................................................................................................... 13 1.1.4: Colored Text..................................................................................................................................... 13 1.2: UNPREDICTABLE and UNDEFINED ....................................................................................................... 13 1.2.1: UNPREDICTABLE........................................................................................................................... 13 1.2.2: UNDEFINED .................................................................................................................................... 14 1.2.3: UNSTABLE ...................................................................................................................................... 14 1.3: Special Symbols in Pseudocode Notation................................................................................................. 15 1.4: Notation for Register Field Accessibility .................................................................................................... 18 1.5: For More Information ................................................................................................................................. 20 Chapter 2: Overview of the MIPS® Architecture................................................................................ 21 2.1: Historical Perspective ................................................................................................................................ 21 2.2: Components of the MIPS® Architecture.................................................................................................... 22 2.2.1: MIPS Instruction Set Architecture (ISA)........................................................................................... 22 2.2.2: MIPS Privileged Resource Architecture (PRA) ................................................................................ 22 2.2.3: MIPS Modules and Application Specific Extensions (ASEs)............................................................ 23 2.2.4: MIPS User Defined Instructions (UDIs)............................................................................................ 23 2.3: Evolution of the Architecture...................................................................................................................... 23 2.3.1: MIPS I through MIPS V Architectures.............................................................................................. 24 2.3.2: MIPS32 Architecture Release 2....................................................................................................... 25 2.3.3: MIPS32 Architecture Releases 2.5+ ................................................................................................ 26 2.3.4: MIPS32 Release 3 Architecture (MIPSr3™).................................................................................... 26 2.3.5: MIPS32 Architecture Release 5....................................................................................................... 27 2.3.6: MIPS32 Architecture Release 6....................................................................................................... 28 2.4: Compliance and Subsetting....................................................................................................................... 30 2.4.1: Subsetting of Non-Privileged Architecture ....................................................................................... 30 2.4.2: Subsetting of Privileged Architecture ............................................................................................... 32 Chapter 3: Modules and Application Specific Extensions ............................................................... 34 3.1: Description of Optional Components......................................................................................................... 34 3.2: Application Specific Instructions ................................................................................................................ 36 3.2.1: MDMX™ Application Specific Extension ......................................................................................... 36 3.2.2: MIPS-3D® Application Specific Extension ...................................................................................... 36 3.2.3: SmartMIPS® Application Specific Extension .................................................................................. 36 3.2.4: MIPS® DSP Module ....................................................................................................................... 36 3.2.5: MIPS® MT Module .......................................................................................................................... 37 3.2.6: MIPS® MCU Application Specific Extension .................................................................................. 37 3 MIPS® Architecture For Programmers Volume I-B: Introduction to the microMIPS32™ Architecture, Revision 6.00 3.2.7: MIPS® Virtualization Module .......................................................................................................... 37 3.2.8: MIPS® SIMD Architecture Module .................................................................................................. 37 Chapter 4: CPU Programming Model.................................................................................................. 38 4.1: CPU Data Formats .................................................................................................................................... 38 4.2: Coprocessors (CP0-CP3).......................................................................................................................... 38 4.3: CPU Registers........................................................................................................................................... 39 4.3.1: CPU General-Purpose Registers..................................................................................................... 39 4.3.2: CPU Special-Purpose Registers...................................................................................................... 39 4.4: Byte Ordering and Endianness.................................................................................................................. 42 4.4.1: Big-Endian Order ............................................................................................................................. 42 4.4.2: Little-Endian Order........................................................................................................................... 42 4.4.3: MIPS Bit Endianness ....................................................................................................................... 42 4.5: Memory Alignment..................................................................................................................................... 43 4.5.1: Addressing Alignment Constraints................................................................................................... 43 4.5.2: Unaligned Load and Store Instructions (Removed in Release 6) .................................................... 44 4.6: Memory Access Types .............................................................................................................................. 44 4.6.1: Uncached Memory Access .............................................................................................................. 45 4.6.2: Cached Memory Access .................................................................................................................. 45 4.6.3: Uncached Accelerated Memory Access ......................................................................................... 45 4.7: Implementation-Specific Access Types..................................................................................................... 46 4.8: Cacheability and Coherency Attributes and Access Types ....................................................................... 46 4.9: Mixing Access Types................................................................................................................................. 47 4.10: Instruction Fetch ...................................................................................................................................... 47 4.10.1: Instruction Fields...........................................................................................................................