ISSN 2322-0929 Vol.02,Issue.01, January-2014, Pages:0018-0025 ww.semargroup.org www.ijvdcs.org Speed Optimized Implementation of 32 Bit RISC (MIPS) Architecture 1 2 KURAMANA HARIKA , SOLOMON J V GOTHAM 1PG Scholar, Dept of ECE, Kaushik College of Engineering, Vishakapatnam, Andhrapradesh, India, E-mail: [email protected]. 2Asst Prof, Dept of ECE, Kaushik College of Engineering, Vishakapatnam, Andhrapradesh, India, E-mail: [email protected]. Abstract: The Implementation of 32 bit RISC processor with microprocessor without interlocked pipeline stages (MIPS) is presented. It was implemented in VHDL so as to reduce the instruction set present in the programmable memory. As the result the processor will contain the necessary logics for the implementation that requires fewer gates to be synthesized in the programmable matrix and has the capability to increase the speed of the target processor with reduced memory. In this paper we propose a novel technique of run-time loading of machine code for MIPS-32 soft-core processor. As we know, implementing fewer instructions on silicon reduces the complexity of the instruction decoder, the addressing logic, and the execution unit. This allows the machine to be clocked at a faster speed, since less work needs to be done each clock period. In this paper we used Xilinx-ISE tool for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and performing placing & routing operation for system verification. Keywords: RISC Processor, MIPS-23, VHDL, Xilinx-ISE. I. INTRODUCTION (almost) completed before the next can be issued for MIPS (originally an acronym for Microprocessor without execution; in a pipelined architecture, successive Interlocked Pipeline Stages) is a reduced instruction set instructions can instead overlap in execution. For instance, computing (RISC) instruction set architecture (ISA) at the same time a math instruction is fed into the floating developed by MIPS Computer Systems (now MIPS point unit, the load/store unit can fetch the next instruction. Technologies). MIPS RISC microprocessor architecture One major barrier to pipelining was that some instructions, characteristics include: like division, take longer to complete and the CPU Fix-length straightforward decoded instruction therefore has to wait before passing the next instruction format into the pipeline. One solution to this problem is to use a Memory accesses limited to load and store series of interlocks that allows stages to indicate that they instructions are busy, pausing the other stages upstream. A major Hardwired control unit aspect of the MIPS design was to fit every sub-phase, A large general purpose register file including cache-access, of all instructions into one cycle, and All operations are done within the registers of thereby removing any needs for interlocking, and the microprocessor. permitting a single cycle throughput. II. MIPS versus RISC Although this design eliminated a number of useful In 1981, a team led by John L. Hennessy at Stanford instructions such as multiply and divide. It was felt that the University started work on what would become the first overall performance of the system would be dramatically MIPS processor. The basic concept was to increase improved because the chips could run at much higher clock performance through the use of deep instruction pipelines. rates. This ramping of the speed would be difficult with Pipelining as a basic technique was well known before interlocking involved, as the time needed to set up locks is (IBM 801 for instance), but not developed into its full as much a function of die size as clock rate. The potential. CPUs are built up from a number of dedicated elimination of these instructions became a contentious sub-units such as instruction decoders, ALUs (integer point. The other difference between the MIPS design and arithmetic and logic), load/store units (handling memory), the competing Berkeley RISC involved the handling of and so on. In a traditional non-optimized design, a subroutine calls. RISC used a technique called register particular instruction in a program sequence must be windows to improve performance of these very common Copyright @ 2013 SEMAR GROUPS TECHNICAL SOCIETY. All rights reserved. KURAMANA HARIKA, SOLOMON J V GOTHAM tasks, but this limited the maximum depth of multi-level opcode; the rest may contain a single 26-bit jump address calls. or it may have up to four 5-bit fields specifying up to three registers plus a shift value combined with another 6-bits of In other ways the MIPS design was very much a typical opcode; another format, among several, specifies two RISC design. To save bits in the instruction word, RISC registers combined with a 16-bit immediate value, etc. This designs reduce the number of instructions to encode. The was one of the major performance improvements that MIPS design uses 6 bits of the 32-bit word for the basic RISC offered. Figure1. Pipelined Datapath III. THE MIPS INSTRUCTION SET instructions or R-type include: ALU Immediate (e.g. addi), ARCHITECTURE three-operand (e.g. add, and, slt), and shift instructions MIPS is a RISC microprocessor architecture. The MIPS (e.g. sll, srl). The J-type instructions are used for jump Architecture defines thirty-two; 32-bit general purpose instructions (e.g. j). Branch instructions (e.g. beq, bne) are registers (GPRs). Register $r0 is hard-wired and always I-type instructions which use the addition of an offset value contains the value zero. The CPU uses byte addressing for from the current address in the address/immediate field word accesses and must be aligned on a byte boundary along with the program counter (PC) to compute the divisible by four (0, 4, 8, …). MIPS only has three branch target address; this is considered PC-relative instruction types: I-type is used for the Load and Stores addressing. instructions, R-type is used for Arithmetic instructions, and Immediate (I-Type) CPU Instruction Format J-type is used for the Jump instructions. Table 1.3.1 provides a description of each of the fields used in the three different instruction types. Jump (J-Type) CPU Instruction Format MIPS is a load/store architecture, meaning that all operations are performed on operands held in the processor registers and the main memory can only be accessed Register (R-Type) CPU Instruction Format through the load and store instructions (e.g lw, sw). A load instruction loads a value from memory into a register. A store instruction stores a value from a register to memory. The load and store instructions use the sum of the offset value in the address/immediate field and the base register Figure2. Shows a summary of the MIPS Instruction in the $rs field to address the memory. Arithmetic Types. International Journal of VLSI System Design and Communication Systems Volume.02, IssueNo.01, January-2014, Pages:0018-0025 Speed Optimized Implementation of 32 Bit RISC (MIPS) Architecture Table1. MIPS Instruction Fields Blocked RAM is a rich resource in modern FPGA chips. It is much easier to design new CPU functions such as adding application specific instruction set and custom data path. The complexity of the sequencing circuits does not increase with the complexity of sequencing logic. By turning sequencing logic into software (micro program), it’s much easier to do a kernel context- switch or update sequencing logic at both design time and run-time. Micro program storage unit is implemented as a Blocked RAM primitive in ECOMIPS. If the microinstruction width is 18bits, a single blocked RAM is able to accommodate 256 micro-instructions on a Xilinx Spartan 3 chip. In most cases, one blocked RAM will be far sufficient for storing the entire micro program. So the sacrifice of one blocked RAM can replace all the sequencing logic which would otherwise use up a large amount of gate resources in FPGA. The microcode in ECOMIPS maps directly to control signals in the data path. Therefore, no translation circuit is needed. However, the speed of reading one word from a blocked RAM is not as fast as that from a combinatorial circuit and the maximum system clock rate of the ECOMIPS is almost linearly dependent on the speed of blocked RAM in the FPGA. Fortunately the speed of RAM access has been made very fast in modern FPGA chips, currently in less than 15 nanoseconds. If the clocking scheme is properly A. Ecomips Architecture designed, the maximum CPU clock rate can still be as high ECOMIPS is a compact 32-bit MIPs CPU module to as 64MHZ. Every MIPS instruction is 32 bits, i.e. one be embedded in a FPGA chip. By taking advantages of word, in length, and every instruction which does not modern FPGA chip, the system itself consumes very little access memory executes in one cycle. Those that do access chip resources and leaves abundant room for implementing memory are assumed to “usually” take two cycles, other specialized control and processing modules. Some of meaning that this will be the case if the desired memory these resources are general purpose ones and used by access results in a cache hit; otherwise, the CPU enters a almost all modules in the chip. However, some resources stall mode until the memory access is satisfied. like multipliers, wide multiplexers, blocked RAM and DCM (with high resolution phase shifting) is not B. Design Implementable Architecture extensively used by most computational modules. When a A 32-bit MIPs CPU module to be embedded in a FPGA specialized FPGA chip is at work, many of its dedicated chip is shown in figure 3.1. By taking advantages of resources are left unused. ECOMIPS takes advantages of modern FPGA chip, the system itself consumes very little those often unused resources and relieves resource racing chip resources and leaves abundant room for implementing on other logic cells on the chip.