INFORMATION TO USERS The most advanced technology has been used to photo­ graph and reproduce this manuscript from the microfilm master. UMI films the original text directly from the copy submitted. Thus, some dissertation copies are in typewriter face, while others may be from a computer printer. In the unlikely event that the author did not send UMI a complete manuscript and there are missing pages, these will be noted. Also, if unauthorized copyrighted material had to be removed, a note will indicate the deletion. Oversize materials (e.g., maps, drawings, charts) are re­ produced by sectioning the original, beginning at the upper left-hand corner and continuing from left to right in equal sections with small overlaps. Each oversize page is available as one exposure on a standard 35 mm slide or as a 17" x 23" black and white photographic print for an additional charge. Photographs included in the original manuscript have been reproduced xerographically in this copy. 35 mm slides or 6" x 9" black and white photographic prints are available for any photographs or illustrations appearing in this copy for an additional charge. Contact UMI directly to order. Accessing the World's Information since 1938 300 North Zeeb Road. Ann Arbor. Ml 48106-1346 USA Order Number 8812232 A standard-cell placement tool for the translation of behavioral descriptions into efficient layouts Buchenrieder, Klaus Juergen, Ph.D. The Ohio State University, 1988 Copyright ©1088 by Buchenrieder, Klaus Jflergen. All rights reserved. UMI 300 N. Zeeb Rd. Ann Arbor, MI 48106 PLEASE NOTE: In all cases this material has been filmed In the best possible way from the available copy. Problems encountered with this document have been identified here with a check mark V 1. Glossy photographs or pages t / 2. Colored Illustrations, paper or print ______ 3. Photographs with dark background ^ 4. Illustrations are poor copy ______ 5. Pages with black marks, not original copy ______ 6. Print shows through as there is text on both sides of p ag e ______ 7. Indistinct, broken or small print on several pages. / 8. Print exceeds margin requirements ______ 9. Tightly bound copy with print lost in spine _______ 10. Computer printout pages with indistinct print _______ 11, Page(s) ___________ lacking when material received, and not available from school or author. 12. Page(s) seem to be missing in numbering only as text follows. 13. Two pages numbered . Text follows. 14. Curling and wrinkled pages Z 15. Dissertation contains pages with print at a slant, filmed as received i / 16. Other A STANDARD-CELL PLACEMENT TOOL FOR THE TRANSLATION OF BEHAVIORAL DESCRIPTIONS INTO EFFICIENT LAYOUTS DISSERTATION Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of the Ohio State University by Klaus Buchenrieder, Dipl. Ing.(FH), M.S. The Ohio State University 1988 Dissertation Committee: Approved by N. Soundararajan P. Sadayappon ✓—TWviser Department of Co'mputer D. Orin and Information Science <1)1988 KLAUS JUERGEN BUCHENRIEDER All Rights R eserv ed To My Parents ACKNOWLEDGMENTS I would like to express my sincere gratitude to my advisor, Professor P. Sadayappan, for his constructive suggestions, encouragement and help during the development of this research. His guidance and support have been invaluable in the completion of this work. I would like to express my appreciation to my formal advisor Professor N. Soundararajan for careful reviewing of the dissertation and for his comments regarding the programming language aspects. I would like to thank Professor D. Orin for his numerous suggestions and for providing access to the MOSIS chip-fabrication facilities. I am also grateful for the opportunity provided by him to participate in his robot-manipulator project os a VLSI- designer. Thanks ore extended to all those very special friends who encouraged and supported me during the years and made it all the more rewarding. I am especially indebted to E. Stavely and Professor K. Schwan for help and encouragement at a critical point in my graduate studies. I am also thankful to M. Kaelbling, for without his assistance this dissertation would still be in the formative stage. I would like to acknowledge the support of the German Fulbright Commission, that granted me a one year’s full-stipend to continue my graduate work here at the Ohio State University. Finally, I wish to express my appreciation to my parents Irene and Fritz, my aunt Maria, and my girlfriend Daniela for their support and patience. VITA June 25,1958 ........................................ Bom - Munich, West Geimany 1978 ................................................. Fachhochschulreife, Staatliche Fachoberschule Muenchen, Fachrichtung Technik 1982 ....................................................... Diplom Ingenieur(FH), Fachhochschule Muenchen, Electrical Engineering, Munich, West Germany 1984 ....................................................... M.S., The Ohio State University, Columbus, Ohio FIELDS OF STUDY Major Field: Computer and Information Sciences Studies in: Computer Architecture and VLSI-Design, with Prof. P. Sadayappan Computer Aided Design, with Prof. V. Ashok Operating Systems, with Prof. K. Schwan Table of Contents ACKNOWLEDGMENTS .......................................................................................... iii VITA ............................................................................................................................. iv LIST OF TABLES ..................................................................................................... vii LIST OF FIGURES ...................................................................................................... viii CHAPTER PAGE I. INTRODUCTION................................................................................................... I n. SURVEY OF RELATED W ORK .............................................................................. 7 1. Introduction , ............................................................................................ 7 2. Layout Design Methods ................................................................................. 7 3. Design with Standard C ells ............................................................................. 19 1. Constructive Placement Techniques ...................................................... 23 2. Iterative Improvement Techniques ........................................................ 25 4. Circuit Transformations ................................................................................. 26 5. Sum m ary........................................................................................................... 23 HI. THE CONSTRUCTIVE PLACEMENT STRATEGY .................................. 30 1. Introduction ....................................................................................................... 30 2. The Basic Design Approach......................... 33 3. The Basic Realization Language ................................................................... 35 1. S y n tax ....................................................................................................... 35 2. Modifications to the B N F ....................................................................... 39 4. Circuit Synthesis.............................................................................................. 41 1. Parsing.. ..................... 41 2. Tree Flattening ........................................................................................ 45 3. Netlist Generation .................................................................................... 48 4. Layout Construction ................... 51 5. Sum m ary........................................................................................................... 54 IV. LAYOUT OPTIMIZATION ........................................................................... 56 1. Introduction ............................................... 56 2. Redundancy Elimination ................................................................................. 58 1. Elimination of Right Recursion .......................................................... 59 v 2. Cascaded Inverter Reduction ................................................................ 63 3. Identifier Merging .................................................................... 68 4. Restructuring ............................................................................................ 71 5. Sinistral Tree Adjustment ....................................................................... 76 6. Common Subexpression Elimination .................................................... 85 3. Peephole O ptim ization .................................................................................... 91 4. Routing Considerations .................................................................................... 97 5. Summary........................................................................................................... 105 V. DESIGN OF STANDARD CELLS..................................................................... 107 1. Introduction ......................... 107 2. Standard Cell Design Frame ........................................................................... 108 3. Complementary CMOS P-Well Technology ............................................... 119 4. Latch-up Prevention .......................................................................................