Module Introduction PURPOSE: The intent of this module is to provide an overview of the MPC5200. OBJECTIVES: - Identify the MPC5200 Block Diagram - Identify the MPC5200 Target Markets - Describe HiP7 Technology - Describe Core Features - Describe System Level Features CONTENT: - 28 pages - 5 questions LEARNING TIME: - 55 minutes The intent of this module is to provide you with an overview of the MPC5200 microcontroller. You will become familiar with the MPC5200 and its target markets. You will also learn about the composition of the MPC5200 by studying its block diagram. Finally, you will explore the core and system level features of the of the MPC5200. 1 MPC5200 Overview Designed with automotive/telematics applications in mind Runs at higher clock, bus, and CPU speeds Handles a tremendous range of applications Welcome to the MPC5200. This processor provides very high performance in automotive and other embedded environments. This device has been designed with automotive and telematics applications in mind. What is new about the MPC5200? Generally, automotive class processors have not run at the clock speeds seen in the MPC5200. The external bus speeds of this device are up to 132 MHz and the internal execution speed for the CPU is up to 400 MHz. This provides the horsepower to do voice recognition, graphics processing and wireless communications. The MPC5200 is not just for automotive applications. In fact, this device will handle a tremendous range of applications. This is mainly due to the wide range of communications peripherals and timers, as well as the processing power provided by the 603 G2_LE core that uses the PowerPCTM instruction set. 2 MPC5200 Block Diagram 16K 32 Entry SystemsSystems Integration ICache MMU IntegrationUnit Unit 16K 16K 32 Entry Memory USB DCach DCache MMU ControllerMemory (Two) e ControllerDDR or (DRAM)SDR Interrupt Control PowerPC603 G2_LE 603e Core Core SDRAM System Functions FPUFPU Real Time clock Chip Selects (6)(8) XLB PCI Controller ROM/SRAM BESTBest BESTBest IPBI ATA/IDE Host Comm 16kB DMA Controller DPRAM JTAG Comm bus IP Bus CAN 2.0 10/100 I2C PSC1 PSC2 PSC3 PSC4 PSC5 PSC6 SPI A/B BaseT J1850 (Two) (Two) Here you can see an MPC5200 block diagram. This microcontroller is composed of the 603 G2_LE processor core, many internal modules, several internal busses, and two external busses. At the heart of the microcontroller is the 603 G2_LE core. The processor core can access all of the internal modules. BestComm, an intelligent Direct Memory Access (DMA) controller, is capable of moving data between various sources and destinations. Many times, the BestComm controller can move data between one of the peripheral elements and memory on either the LocalPlus or SDRAM bus without interfering with the CPU’s fetching of instructions. There is a wide range of communications modules that provide different communication formats. This course will provide you with an understanding of all the internal bus structures, the internal peripheral modules, the CPU core, the BestComm controller and the external bus structures. 3 MPC5200 Block Diagram SDRAM BUS 16K 3232 Entry SystemsSystems Integration ICacheICache MMU IntegrationUnit Unit 16K 16K 3232 Entry Memory USB DCach DCache MMU ControllerMemory (Two) e ControllerDDR or (DRAM)SDR Interrupt Control PowerPC603 G2_LE 603e core Core SDRAM System Functions FPU Real Time clock Chip Selects (6)(8) XLB PCI Controller ROM/SRAM LOCALPLUS SmartBest Smart IPBI ATA/IDE Host BUS Comm 16kB DMA Controller DPRAM JTAG Comm bus IP Bus CAN 2.0 10/100 I2C PSC1 PSC2 PSC3 PSC4 PSC5 PSC6 SPI A/B BaseT J1850 (Two) (Two) The MPC5200 has a very high level of integration. There are two external data/address bus structures, the SDRAM bus and the LocalPlus bus. The LocalPlus bus can perform normal memory accesses, Advanced Technology Attachment (ATA) cycles, and Peripheral Component Interconnect (PCI) cycles. There is a wide range of peripherals that provide for many different types of serial communications. For instance, there are six Programmable Serial Controllers, a Serial Peripheral Interface, 10 and 100 Mbit Ethernet, J1850, two I2C modules, two MSCAN modules and two USB channels. In the System Integration Unit, there is a Real Time Clock, the Interrupt Control Logic, the Chip Select Logic, and an 8 channel Timer module. Click “MPC5200 Features” to learn about the main features of the MPC5200 microcontroller. 4 MPC5200 Features Features • 603e series PowerPC Core 16K Instruction and 16K Data Caches Dual 32 Entry MMUs • High Speed SDRAM interface 256Mbyte addressing range, 32-bit wide (per Chip Select Line) 2 Chip selects • Flexible multi-function external bus PCI master v2.2, ATA v4 compatibility • SmartComm I/O subsystem Support for PSC, Ethernet, PCI, ATA, IrDA, I2C, AC97, SPI on PSC, LPC 16kB internal SDRAM • 6 Peripheral Serial Controllers UART, AC97, I2S ( PSC1-3+6) • Superior system integration for DIS CAN, Serial, USB, J1850 Power Management • Nap, Doze + Sleep modes • Deep Sleep Package • 272 pin PBGA, 1.27mm pitch Reference info for previous page 5 MPC5200 Target Markets Gateways and Network Edge Devices (Ethernet and USB) Industrial Control (Ethernet and CAN) Video Detection & Biometrics Processing Electronic and Medical Instrumentation GPS Processing Telematics and Automotive (CAN, J1850) The MPC5200 can be used in a wide range of target markets. Because it is manufactured in HiP7 (or HiPerMOS7) technology, the device yields very high speed circuitry with very small die size. In other words, this device presents a very attractive price to performance ratio. The 603 G2_LE core implements the PowerPC™ instruction set. Along with the internal Floating Point Unit and high speed internal clock speed, the MPC5200 can handle high speed communications tasks, video, Global Positioning, and other jobs that require significant processing power. 6 Question Indicate whether the sentence below is True or False. The MPC5200 can be used in a wide range of target markets. Because it is manufactured in HiP7 technology, this device is very high speed with very small die size. •True •False You have just learned a bit about the MPC5200. Now let’s review some of the material we have covered so far with a question. Answer: The MPC5200 is used in a wide range of target markets. It is very high speed with a small die size. This means that this device presents a very attractive price to performance ratio. 7 Development tools today Compiler : CodeWarrior www.Freescale.com Debugger : Abatron probe http://www.abatron.ch/ Lauterbach probe http://www.lauterbach.com Isystem http://www.isystem.com Operation systems : QSSL QNX http://www.qnx.com OSE systems http://www.ose.com/prodserv/esp/ OSEK www.Freescale.com Evaluation boards : Total5200 Development Platform Lite5200 Evaluation Board a general market EVM system (March 2002) Windriver, Lineo. Now let’s look at development tools. You can find information on the latest tools such as compilers, debuggers and operating systems at the web sites listed above. Future developments partnerships include Wind River and Lineo. 8 EVB/Development Platforms Best in Class Total5200 Lite5200 Evaluation Board (EVB) Development Platform Committed RTOS/SW Support Application SW Support •CodeWarrior Compiler/Debugger •Bluetooth SW Stack •Freescale Linux Solution •Voice Rec/Text to Speech •QSSL QNX •AEC/Noise Suppression •Green Hills Integrity •PowerPC Applications •Wind River VxWorks •MontaVista Linux Emulation HW Support •IBM Websphere/J9 Abatron, Lauterbach, PowerTap Here you can see images of the Total5200 Development Platform and the Lite5200 Evaluation Board (EVB). Support for the 5200 series chips are outlined in the graphic. You can see this includes software application and emulation support. 9 Lite5200 EVB 400 MHz Lite5200 Board • 160mm x 133mm • 64 MB SDRAM, 8 MB Flash (Can support 16 MB Flash in future) • PC104+(PCI), ATA • CAN (2), USB, I2C (2) • 1UART • 10/100 Ethernet • All additional MPC5200 I/O available on header connector • No MOST, LCD Controller, Head Unit, Audio Subsystem • No Integrated 12V Power Support Lite5200 Software • CodeWarrior 30-day Eval Seat • dBug - low level debugger & boot loader • Evaluation copies of Green Hills, MontaVista, QNX and Wind River • Available July, 2003 Reference info for previous page. 10 Total5200 400 MHz Total5200 Development Platform • Base unit - 1 DIN Form Factor • 120VAC or 11-14VDC • 64MB SDRAM, 64MB Flash • PC104+(PCI), ATA • 2 CAN, MOST, 2 USB, I2C •9 UARTs • LCD controller w/ VGA & S-Video (Epson S1D13806) • 10/100 Ethernet • Audio Inputs/Outputs supporting Mic, Bluetooth, Radio, BigFoot Phone & Speaker. 1 RS-232 CRT Total5200 HeadUnit USB Ethernet S-Video • Detachable, Graphics Touchscreen • Reconfigurable buttons Evaluation Software/Tools • CodeWarrior • QNX Momentics and IBM WebSphere/ J9 JVM 2 • Green Hills, MontaVista, Wind River evaluation BSPs Mic1 Mic2 being planned Phone Radio L Radio Radio R Line1 (DSP) Line1 Headphone Line2 (MP3) Line2 • dBug - low level debugger & boot loader (Video) Line3 Bluetooth ™ Loudspeaker , L , Loudspeaker • Available July, 2003 , R Loudspeaker Reference info for previous page. 11 HiP7 Technology Is Freescale’s densest, highest performance, most modular, and lowest power System-on-Chip platform process to date Contains minimum features of 0.065 micron Enables system-on-chip solutions for applications spanning low power wireless to high performance networking and computing products. Provides a means to manufacture complex chips that are economically