Calcolatori Elettronici e Sistemi Operativi CISC Complex Instruction Set Computer Goals CPU Reduced semantic gap (programming language / cpu instructions) examples Reduced code size Strategies Complex instructions Large number of address modes Memory based operations Special instructions for control flow Variable length instructions CISC CISC Complex instructions Memory based operations Multi-cycle decoding e.g: add eax,[ebx] Multi-cycle execution Complex control Complex control Special instructions for control flow Large number of address modes loops Complex modes function call and return e.g., pointer dereferencing Complex control e.g., vector access: mov eax,[4*ebx+esi] Variable length instructions Complex control Smaller codes for most used instructions Multi-cycle fetch Complex control CISC RISC Complex control Reduced Instruction Set Computer Microprogrammed Goals Pipelining High speed (high throughput): 1 instruction for cycle at microinstruction level Simple control Strategies Examples Restricted memory access: load and store IBM System/360, VAX, PDP-11, Motorola 680x0, Intel x86 Few addressing modes (and simple) Fixed-size instruction formats Homogeneous register usage (mostly) Regular datapath RISC RISC Restricted memory access: load and store Homogeneous register usage (mostly) load and store only Simple control Data operations only through registers Regular datapath Simple control Simple control Few addressing modes (and simple) Instructions are mapped on datapath operations Simple control 1 instruction => 1 datapath operation Fixed-size instruction formats Single-cycle decoding Single-cycle fetch Single-cycle execution Simple control Simple control RISC RISC history Simple control RISC David Patterson (Berkeley, 1980) Simple development Register window Hardwired control (no µ-program) 128 registers – 8 registers addressable at a time RISC I Saved area 32 instructions More registers RISC II Reduced memory access frequency 39 instructions Cache evolved in SUN SPARC Reduced average memory access latency Harvard architecture MIPS John Hennessy (Stanford, 1981) Large semantic gap Microprocessor without Interlocking Pipeline Stages covered by compilers RISC history Typical operations ARM Data transfer Load / Store Acorn Computers Ltd (Cambridge, 1983-1985) Move Acorn RISC Machine Exchange Advanced RISC Machines Ltd Push / Pop ARM Ltd Input / Output IBM PowerPC Data manipulation IBM 801 (1975) America project (1985) PowerPC (1990) Arithmetic ADD / SUB / INC / DEC / MUL / DIV / ADC /SBB / NEG / CMP / TST Logic HP PA-RISC CLR / SET / NOT / AND / OR / XOR / CLflag / SETflag HP Precision Architecture RISC Shift 1986 SHL / SHR / SLA / SRA / ROL / ROR / RLC / RRC Floating Point DEC Alpha 1992 Flow control 64-bit B (o J) / JMP / CAL (o JSR) / RET / INT / RTI / SKP.