Louisiana State University LSU Digital Commons LSU Historical Dissertations and Theses Graduate School 1986 A Horizontally Reconfigurable Architecture for Extended Precision Arithmetic (Parallel Computing, Condition Codes Factoring). Donald Mark Chiarulli Louisiana State University and Agricultural & Mechanical College Follow this and additional works at: https://digitalcommons.lsu.edu/gradschool_disstheses Recommended Citation Chiarulli, Donald Mark, "A Horizontally Reconfigurable Architecture for Extended Precision Arithmetic (Parallel Computing, Condition Codes Factoring)." (1986). LSU Historical Dissertations and Theses. 4178. https://digitalcommons.lsu.edu/gradschool_disstheses/4178 This Dissertation is brought to you for free and open access by the Graduate School at LSU Digital Commons. It has been accepted for inclusion in LSU Historical Dissertations and Theses by an authorized administrator of LSU Digital Commons. For more information, please contact [email protected]. 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Further reproduction prohibited without permission. 8625329 Chiarulli, Donald Mark A HORIZONTALLY RECONFIGURABLE ARCHITECTURE FOR EXTENDED PRECISION ARITHMETIC The Louisiana State University and Agricultural and Mechanical Col. Ph.D. 1986 University Microfilms International300 N. Zeeb Road, Ann Arbor, Ml 48106 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. PLEASE NOTE: In all cases this material has been filmed in the best possible way from the available copy. Problems encountered with this document have been identified here with a check mark V . 1. Glossy photographs or pages_____ 2. Colored illustrations, paper or print______ 3. Photographs with dark background_____ 4. Illustrations are poor copy______ 5. Pages with black marks, not original copy______ 6. Print shows through as there is text on both sides of page_______ 7. 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A HORIZONTALLY RECONFIGURABLE ARCHITECTURE FOR EXTENDED PRECISION ARITHMETIC A Dissertation Submitted to the Graduate Faculty of the Louisiana State University and Agricultural and Mechanical College in partial fulfillment of die requirements for the degree of Doctor of Philosophy in The Department of Computer Science by Donald Mark Chiarulli B.S., Lousiana State University, 1976 M.S., Virginia Polytechnic Institute, 1979 August 1986 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Acknowlegments I must begin by expressing my deep appreciation to Dr. Walter G. Rudd, committee chairman, mentor, and friend of many years. None of this would have happened had it not been for his ideas, support, advice, and encouragement Thanks also to Dr. Duncan A. Buell whose problems in number theory provided the motivation for this work and to Dr. S Sitharama Iyengar who was the catalyst for die non-numeric applications of this architecture. To Dr. Powsiri Kiinkhachom, thanks for helping to smooth out the glitches. Thanks also to Dr. Donald Kraft for his excellent editorial assistance in the preparation of this document Finally, my deepest appreciation must go the the undergraduate and graduate stu­ dent members of the DRAFT Architecture Research Group. They are too numerous to mention, but have over the past two years freely made the committments and sacrifices necessary to bring this project from an idea to reality. May the rest of their careers be as successful as they have made this project ii Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. Table of Contents CHAPTER 1 INTRODUCTION AND MOTIVATION 1.0 Introduction ....................................................................................................... 1 1.1 Related Research............................................................................................... 7 CHAPTER 2: THE DRAFT ARCHITECTURE 2.0 Overview ........................................................................................................... 14 1.1 Host Processor .................................................................................................. 19 2.2 Sequencer .......................................................................................................... 22 2.2.1 Clocking and Pipeline Organization ............................................................... 22 2.2.2 Instruction Sequencing .................................................................................. 24 2.2.3 Data RAM Page Addressing ........................................................................... 25 2.2.4 Global Condition Multiplexing ....................................................................... 27 2.2.5 Segmentation Control .................................................................................... 28 2.3 ALU Slices............................................................!........................................ 29 2.3.1 Arithmetic and Logic ..................................................................................... 29 2.3.2 Status Multiplexing ........................................................................................ 31 2.3.3 Special Handling of Zero Status ..................................................................... 32 2.3.4 Shift Multiplexer............................................................................................ 33 2.3.5 Write Enable Multiplexer .............................................................................. 33 2.3.6 Resolving Data Memory Addresses ............................................................... 34 2.4 Cany Look Ahead ............................................................................................ 34 2.5 A Long Word Length Hardware Multiplier _____________________ 36 Chapter 3: PARALLEL MICROPROGRAMMING TOOLS 3.0 Overview .......................................................................................................... 38 3.1 The DRAFT micro-assembler........................................................................... 38 3.1.1 Segmentation register, the SEG statement ...................................................... 42 3.1.2 The DATAPAGE statem ent........................................................................... 43 3.1.3 ALU operation register, the OP statement ...................................................... 44 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 3.1.4 Shifter operation register, the SHIFT statement .............................................. 46 3.1.5 Local condition codes, the COND statement _______________ 47 3.1.6 Sequencer instruction fields .................. 47 3.1.7 Comments ............. 48 3.1.8 A Programming Example ________________________________