Freescale Semiconductor AN2692 Application Note Rev. 0.2, 9/2004 MC9S12NE64 Integrated Ethernet Controller By Steven Torres 8/16 Bit System Engineering Austin, Texas Introduction Ethernet connectivity of embedded devices is a growing trend in industrial and consumer applications. Ethernet is a medium of choice because of its competitive performance, relatively low price of implementation, established infrastructure, and interoperability. Ethernet is also easy to use, widely available, and scalable. With Ethernet capability, embedded devices can be connected to the Internet, which allows access to the embedded device from across the world. Figure 1 shows a simplified illustration of an embedded device that is connected, transparently, to a remote host by the Internet. EMBEDDED DEVICE CONTROL INTERNET BOARD MOTOR REMOTE HOST Figure 1. Embedded Device on Internet ® This product incorporates SuperFlash technology licensed from SST. © Freescale Semiconductor, Inc., 2004. All rights reserved. Introduction The MC9S12NE64 is a 16-bit MCU based on Freescale Semiconductor’s HCS12 CPU platform. It is the first in a series of low-cost Ethernet-capable MCUs in a small package. The MC9S12NE64 provides a complete, integrated, single-chip Ethernet solution. This application note provides a system overview of the MC9S12NE64 and its integrated Ethernet controller. This discussion also describes how the MC9S12NE64 fits into the network communication model of wired networks. This discussion describes detailed setup for register configuration, initialization, and operation regarding the MC9S12NE64 Ethernet capability; however, Freescale Semiconductor provides a free software driver for the MC9S12NE64 Ethernet controller, which greatly simplifies its setup and use. See EMAC and EPHY sections for details. Connectivity Example Applications Embedded devices with Ethernet capability can be implemented in a wide range of applications, including: • Database data logging or queries • Web servers for remote embedded devices • Remote monitoring (data collection/diagnostics) • Control of remote devices • Use of email by remote device • Remote reprogramming of nonvolatile memory (FLASH) The MC9S12NE64 provides a total solution for systems that: • Need Ethernet connectivity • Are end nodes on a network • Need Ethernet connectivity, but not necessarily the fastest data throughput • Need a low-cost Ethernet solution • Need a reduced component count and package size Ethernet Network Overview This section provides an overview of Ethernet basics and discusses how the MC9S12NE64 fits into the network communication model of wired Ethernet networks. Ethernet is commonly used in local area networks (LANs) for device connectivity because it is inexpensive and fast. Ethernet is a technology used in LANs where a group of network devices share a common communications medium. In this application note, the focus is wired LANs because the MC9S12NE64 is designed for wired LANs. The most common communications medium, for wired LANs, is category 5 (cat- 5) un-shielded twisted pair (UTP) cable. Using Ethernet technology and the shared communications medium allows the sharing of resources and data among connected devices on the network. Wired Ethernet is becoming a widely used communication tool much like an SCI or USB. The IEEE 802.3™ standard defines how wired Ethernet works. Ethernet works on the basis that every device connected to the network has a unique hardware address. Because Ethernet uses a shared medium, when one device transmits an Ethernet packet on the network (an Ethernet packet as defined in the IEEE 802.3 standard is shown in Figure 2), every device on the network sees that message. Each device on the network starts to process the packet to determine whether the packet is meant for it by MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2 2 Freescale Semiconductor Introduction inspecting the incoming Ethernet packet destination hardware address. Depending on the destination hardware address of the incoming packet, the device will either ignore the message or accept it for further processing. 7 BYTES PREAMBLE 10101010 1 BYTES START DELIMITER 10101011 MAC HEADER DESTINATION 6 BYTES MAC ADDRESS SOURCE 6 BYTES MAC ADDRESS 2 BYTES LENGTH/TYPE DATA FIELD ENCAPSULATED DATA 46 TO 1500 (LAYER 3 AND UP) BYTES PAD FIELD FRAME CHECK MAC TRAILER 4 BYTES SEQUENCE Figure 2. Format and Content of Ethernet Packets Ethernet Packet Figure 2 illustrates the specific structure of an Ethernet packet. Figure 2 shows that the data field of an Ethernet packet is encapsulated by a media access controller (MAC) header and frame check sequence (FCS) trailer. It is important to understand the format and content of Ethernet packets that are transferred between devices in a typical LAN because Ethernet devices operate on these data fields. The data fields are: • MAC Header – Preamble — Seven bytes of an alternating pattern of 1s and 0s that indicates that a frame is coming and provides synchronization. – Start of frame delimiter (SFD) — One byte that follows the preamble and consists of an alternating pattern of 1s and 0s that ends with two consecutive 1s. – Destination MAC address (or hardware MAC address) — 6-byte value that indicates the MAC hardware address of the network device that should receive the Ethernet packet. – Source MAC address (or source hardware address) — 6-byte value that indicates the MAC hardware address of the network device that is sending the Ethernet packet. – Length/type — 2-byte value that indicates the number of data bytes that are encapsulated by the Ethernet packet if the length/type value is less-than or equal-to 1500. If the length/type field is greater than 1536, the length/type field identifies the type (or Ethertype) of the packet. The Ethertype identifies the higher-level protocol used to create the encapsulated data portion of an Ethernet packet. MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2 Freescale Semiconductor 3 Introduction • Encapsulated data portion — 46 to 1500 bytes of user data. • Frame check sequence trailer (frame check sequence) — 4-byte value that contains a 32-bit cyclic redundancy check (CRC) value. Ethernet is not the only component of the communication mechanism required for LAN operation. Figure 3 provides a more complete look at the communication model used by a generic user application that uses LAN. The network interface block is where Ethernet is positioned in the LAN communication model. Figure 3 shows that the simplified block version provided is actually derived from a TCP/IP model, which in turn is derived from ISO’s (the International Organization for Standardization) OSI (open systems interface model) 7-layer theoretical communications model. ISO’S OSI MODEL TCP/IP MODEL USER APPLICATION APPLICATION API 7 APPLICATION HTTP, TFTP, SMTP, 6 PRESENTATION APPLICATION DHCP, SNMP, etc... 5 SESSION SOCKET API TCP STACK SOFTWARE 4 TRANSPORT TRANSPORT TCP, UDP IP, ARP, ICMP 3 NETWORK NETWORK DEVICE DRIVER API 2 DATA LINK LINK NETWORK INTERFACE ETHERNET CONTROLLER 1 PHYSICAL AND PHYSICAL INTERFACE NETWORK Figure 3. Block Diagram of TCP/IP Stack Model The functionality that the data link layer and the physical layer provides to the LAN communication model is very important. These layers work together to provide access to the analog world of the UTP cable. The following bullets list some of the basic functions performed by the data link layer and the physical layer. • Data link layer — MAC – Packet error checking – Data framing – Network access • Physical layer — PHY – Analog signaling This document will provide a brief overview of TCP/IP stack software, but TCP/IP stack software is not the focus of this document. MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2 4 Freescale Semiconductor MC9S12NE64 Integrated Ethernet Controller MC9S12NE64 Integrated Ethernet Controller This section will introduce the MC9S12NE64 and provide an overview of the MC9S12NE64 integrated Ethernet controller. The discussion will also include a summary of the minimum number of printed circuit board (PCB) components required in an MC9S12NE64 system to enable its Ethernet capability. MC9S12NE64 The MC9S12NE64 includes 8K of RAM and 64K of FLASH. It also has other standard on-chip peripherals, including two asynchronous serial communications interface modules (SCIs), a serial peripheral interface (SPI), an inter-integrated circuit module (IIC), a 4-channel/16-bit timer module (TIM), an 8-channel/10-bit analog-to-digital converter (ATD), and pins available as keypad wake-up inputs (KWUs). In addition, in the 112-pin package, an expanded bus that is specified for operation at 16 MHz1 is available. Integrated Ethernet Controller The MC9S12NE64 introduces a new peripheral for the HCS12 CPU platform, an integrated Ethernet controller. The MC9S12NE64 integrates an Ethernet controller that includes a MAC and PHY in one die with the CPU, memory, and other HCS12 standard on-chip peripherals. The MC9S12NE64 can be targeted at low-throughput connectivity applications that use a 3.3-V external power supply. With an on-chip bandgap-based voltage regulator (VREG), an internal digital supply voltage of 2.5 V (VDD) can also be generated. A block diagram of the MC9S12NE64 is provided in Figure 4. More information on the MC9S12NE64 is available from the Freescale Semiconductor website: http://freescale.com. 1. At a 16-MHz internal bus speed, the MC9S12NE64 integrated Ethernet controller is limited to 10-Mbps operation. A 25-MHz internal bus speed is required for 100-Mbps