NANOCHIP Technology Journal INTEGRATING ATOMIC LAYER DEPOSITION HIGH-κ DIELECTRICS IN THIS ISSUE • Advanced Transistors—Scaling with New Materials and New Architecture • Spike Anneals for 32nm and Beyond • Nano-Porous Dielectrics for 28nm Applications volume 9, issue 2, 2011 A MESSAGE FROM KLAUS SCHUEGRAF Table of Contents Corporate Vice This is an exciting time in our industry, spurring the technical advances highlighted 3 Advanced Transistors — President and CTO, in this issue. With planar transistor scaling facing a growing number of limitations, Scaling with New Materials and New Architecture Silicon Systems Group we seek a new degree of freedom by going three-dimensional, while continuing to pursue solutions that extend planar scaling to its ultimate extent. The 2x nanometer 10 Optimizing Spike Anneals era requires bold changes in device architectures, introducing a significant increase in for 32nm and Beyond complexity throughout the manufacturing flow. At the 2x nanometer node, logic devices require high-k/metal gate architecture, 15 Integrating Atomic Layer Deposition High-κ Dielectrics introducing additional process steps and much more stringent process requirements. at the ≤22/20nm Logic Technology Node Equivalent oxide thickness scaling and gate leakage challenges drive the need for atomic layer deposition (ALD) of high-k dielectric gate stacks. Turning attention to source/drain regions, we discuss solutions to 20 Extending Oxynitride Gate Technology thermal pattern loading effects in rapid thermal processing (RTP), which is particularly critical in the formation for Advanced DRAM of shallower junctions without compromise to activation. 25 Improving Tungsten Chemical Mechanical Planarization As DRAM devices scale below the 3x nanometer node, a new deep plasma process is required to enable for Next-Generation Applications higher-dose nitridation without increasing leakage current or the magnitude of transistor threshold voltage. Tungsten CMP applications in memory now require real-time process control for greater precision and flatness 29 A High Productivity ALD-Like Conformal Oxide Liner uniformity, and benefit from dual-wafer polishing with its significantly lower cost of consumables. for ≤20nm Technology Nodes Scaling is also driving breakthroughs in the interconnect. We discuss a third-generation low-k dielectric with uniform porosity, which boosts mechanical strength over previous generations and lowers the dielectric 35 Optimizing Nano-Porous Dielectrics constant to 2.2. We also discuss a new tuning parameter for achieving etch depth uniformity and CD control for ≤28nm Applications needed for uniform resistance of copper interconnect lines. I expect these articles will interest you, and I am encouraged by our ongoing engagements as we all innovate to 43 Enhancing Dielectric Etch Uniformity enhance the technical expertise, productivity, and efficiency of our industry. for 28nm Copper Dual Damascene Front Cover: To extend Moore’s law to the 2x nm node and beyond, logic devices require high-k/metal gates; the high-k dielectric is actually a stack of several layers, with atomic layer deposition (ALD) used to deposit the ultra-thin high-k layer. Integrating the ALD process on a single platform with low-temperature radical oxidation, nitridation, and post-nitridation anneal chambers enables the high-k dielectric to be optimized, minimizing queue-time between each step and keeping the wafer in a controlled vacuum environment for the entire sequence. This avoids contamination and prevents degradation of the interfaces in this critical core of the transistor. Table of Contents 3 Advanced Transistors — Scaling with New Materials and New Architecture 10 Optimizing Spike Anneals for 32nm and Beyond 15 Integrating Atomic Layer Deposition High-κ Dielectrics at the ≤22/20nm Logic Technology Node 20 Extending Oxynitride Gate Technology for Advanced DRAM 25 Improving Tungsten Chemical Mechanical Planarization for Next-Generation Applications 29 A High Productivity ALD-Like Conformal Oxide Liner for ≤20nm Technology Nodes 35 Optimizing Nano-Porous Dielectrics for ≤28nm Applications 43 Enhancing Dielectric Etch Uniformity for 28nm Copper Dual Damascene ADVANCED TRANSISTORS Scaling with New Materials and New Architecture KEYWORDS Classic transistor scaling has given way to modern scaling field effect transistor) can offer a step function im- Transistor and related performance enhancement based on new provement in transistor performance with substantially 3D materials in strain engineering and high-κ metal gate higher carrier mobilities and lower operating voltages.[6] schemes. Next-generation devices will incorporate an FinFET Structural building blocks of a MOSFET transistor are even wider range of new materials and three-dimensional QWFET transforming radically (Figure 1). This review examines transistor architectures to sustain Moore’s Law; these HKMG the evolution of each to meet today’s and tomorrow’s trends are posing challenges that are driving development Isolation needs. of new process capabilities in transistor fabrication. Channel Figure 1 Gate Stack Over the past 40 years, transistors have undergone Classic MOSFET (130nm) Source/Drain steady miniaturization in accordance with Moore’s Silicide Epitaxial Growth Law. Until the 130nm node, referred to as the classic or Denard era, scaling followed a set of simple rules RTP Anneal Poly to shrink gate length, gate dielectric thickness, and Spacer Shallow Junction junction depth by a factor 1/k (k~1.4).[1] The 90nm node SiON Strain Engineering transistor to the present, referred to as the modern Source Drain MOSFET (metal oxide semiconductor field effect transistor) era, has seen the non-classical adoption of (a) Figure 1. (a) Classic new materials to sustain scaling. For the 22nm node Modern MOSFET (32nm) (130nm) MOSFET and and beyond, we expect an even greater adoption of new (b) modern (32nm) MOSFET materials and architectures. showing application of Metal newer materials for strain The classic era efficiently provided for the needs of that time in higher circuit speeds and higher densities. But High-κ engineering and high-κ metal Spacer WF Metal the modern era imposes multiple demands for lower gate. SiON Liner active and passive power, and higher speed and packing Epi Epi Source Drain density. Many innovations in new materials have been responses to these multiple demands. Strain engineering through epitaxial source-drain structures increased (b) carrier mobility in the channel and enabled higher speeds.[2] At the 45nm node, high-κ metal gates ISOLATION substantially reduced active power via leakage from gate While the active silicon pitch and shallow trench isola- to channel.[3] The 3D FinFET (fin field effect transistor) tion (STI) widths decrease proportionally with scaling, transistor at the 22nm node is a new architecture that STI depth is decreasing only incrementally. According substantially reduces passive power or active power to the 2009 ITRS, STI top width will decrease from while enabling advanced transistor scaling.[4] New 59nm in 2009 to 28nm in 2015, but the trench depth substrates, such as FDSOI (fully depleted silicon-on- will decrease only from 353nm to 309nm. As a result, insulator), are designed for lower operating power and the STI aspect ratio will grow from 6:1 to 11:1, increasing higher performance benefits.[5] New channel materials the challenge for void-free STI fill. A series of chemical incorporated in a QWFET architecture (quantum well vapor deposition (CVD) oxide processes has been 3 Volume 9, Issue 2, 2011 Nanochip Technology Journal Applied Materials, Inc. Evolving Transistor Technologies developed to meet fill challenges: from high-density CHANNEL plasma (HDP) to sub-atmospheric CVD (SACVD), Much recent research has been directed at new to high aspect ratio process (HARP) CVD, to today’s channel materials: SiGe,[8] Ge,[9] III-V compound eHARP, and flowable CVD solutions. HDP has good film semiconductors,[10] carbon nanotubes,[11] and quality and low wet etch rate ratio (WERR) as deposited, grapheme.[12] Among them, III-V and Ge materials are while other films require optimized post-deposition front runners given their greater maturity through adop- anneal to improve film quality and reduce WERR. HDP tion in optoelectronic and communication devices and is capable of void-free STI fill up to an aspect ratio of in logic devices today. Other candidates face a “bottom approximately 5:1. HARP and eHARP are currently up synthesis” challenge requiring a different alignment standard films for STI fill, while flowable CVD with its approach than established etch and patterning.[13] outstanding bottom-up fill capability will be used for III-V materials, such as InSb or InAs, can theoretically the n+1 node and beyond. provide 50-100 times the electron mobility of silicon and For 3D FinFET transistors, a critical process step is Ge provides higher hole mobility than silicon, making recessing the STI oxide to form the “fin” (Figure 2). them attractive candidates for NMOS and PMOS, [14] Standard wet etching, dry plasma etching, or plasma- respectively. A possible architectural construct for free dry oxide removal processes can be employed. implementing these new channel materials is a QWFET The latter iterates between growth and sublimation of transistor derived from a HEMT (high electron mobility [14] ammonium fluorosilicate with each cycle, consuming transistor) device. Here the active channel layer is a well-controlled amount of oxide (e.g.,