Emerging Technologies in On-Chip and Off-Chip Interconnection Network A thesis presented to the faculty of the Russ College of Engineering and Technology of Ohio University In partial fulfillment of the requirements for the degree Master of Science Md Ashif Iqbal Sikder August 2016 © 2016 Md Ashif Iqbal Sikder. All Rights Reserved. 2 This thesis titled Emerging Technologies in On-Chip and Off-Chip Interconnection Network by MD ASHIF IQBAL SIKDER has been approved for the School of Electrical Engineering and Computer Science and the Russ College of Engineering and Technology by Avinash Karanth Kodi Associate Professor of Electrical Engineering and Computer Science Dennis Irwin Dean, Russ College of Engineering and Technology 3 Abstract SIKDER, MD ASHIF IQBAL, M.S., August 2016, Electrical Engineering Emerging Technologies in On-Chip and Off-Chip Interconnection Network (80 pp.) Director of Thesis: Avinash Karanth Kodi The number of processing cores on a chip is increasing with the scaling down of transistors to meet the computation demand. This increase requires a scalable and an energy and latency efficient network to provide a reliable communication between the cores. Traditionally, metallic interconnection networks are used to connect the cores. However, according to the International Technology Roadmap for Semiconductor (ITRS), metallic interconnection networks would not be able to meet the future on-chip communication demands due to the energy and latency constraints. Thus, this thesis focuses on the novel on-chip network designs employing the emerging technologies, such as wireless and optics, to provide a scalable and an energy and latency efficient network. In this thesis, I propose an on-chip network architecture called Optical and Wireless Network-on-Chip (OWN) and extend OWN to construct Reconfigurable Optical and Wireless Network-on-Chip (R- OWN) architecture. OWN and R-OWN both leverage the advantages of optics and wireless technologies while circumventing the limitations of these technologies. The end result is that OWN and R-OWN both can provide a maximum of three hops communication between any two cores for a 256 to 1024 core networks. My simulation results with synthetic traffic demonstrate that, for 1024-core architectures, OWN requires 34% more area than hybrid-wireless architectures and 35% less area than hybrid-photonic architectures [1]. In addition, OWN consumes 30% less energy per bit than hybrid-wireless architectures and 14% more energy per bit than hybrid-photonic architectures [1]. Moreover, OWN shows 8% and 28% improvement in saturation throughput compared to hybrid-wireless and metallic architectures respectively [1]. On the other hand, for 256-core architectures, R-OWN requires 3.9% and 12% less area compared to metallic and hybrid-wireless 4 architectures respectively. Additionally, R-OWN consumes 44% and 50% less energy per bit compared to metallic and hybrid-wireless architectures respectively. Furthermore, R- OWN shows saturation throughput that is 27% and 31% higher than hybrid-wireless and metallic architectures respectively. Since the number of memory intensive applications is increasing, similar to on-chip communication off-chip memory access is also becoming important. A metallic link is gen- erally used to connect the on-chip components to the off-chip memory element. Because wireless technology shows a better energy efficiency and latency requirement compared to the metallic technology for longer distances, in this thesis, I propose several hybrid-wireless networks to explore the use of wireless technology, as an alternative to the metallic technol- ogy, for off-chip memory access. My proposed networks require a maximum of two hops to access the off-chip memory and also significantly reduce both the application execution time and energy per bit for real traffic. My simulation results show that, for a 16-core net- work, the on-chip and off-chip wireless network requires 11% less execution time and also consumes approximately 79% less energy per packet compared to the baseline metallic ar- chitecture. 5 Acknowledgements First, I would like to thank my parents for always supporting me. Second, I would like to thank my supervisor Dr. Avinash Kodi, for relentlessly pushing me. Third, I would like to thank my committee members- Dr. Savas Kaya, Dr. Jeffrey Dill, and Dr. David Ingram for their valuable time. Lastly, I would like to thank NSF as this thesis work was partially supported by NSF grants CCF-1054339 (CAREER), CCF-1420718, CCF-1318981, ECCS- 1342657, and CCF-1513606. 6 Table of Contents Page Abstract.........................................3 Acknowledgements...................................5 List of Tables......................................8 List of Figures......................................9 List of Acronyms.................................... 10 1 Introduction..................................... 11 1.1 Network-on-Chip (NoC)........................... 12 1.2 Issues in NoC................................. 15 1.2.1 Energy................................ 15 1.2.2 Latency................................ 16 1.2.3 Metallic Interconnects........................ 16 1.3 Emerging Technologies in Interconnection Network: Wireless and Photonics 17 1.3.1 Wireless Interconnection Network.................. 17 1.3.2 Photonic Interconnection Network.................. 20 1.4 Proposed Research and Major Contributions................. 22 1.4.1 Heterogeneity in Interconnection Network.............. 23 1.4.2 Off-Chip Interconnection Network.................. 24 1.4.3 Key Contributions and Thesis Organization............. 25 2 Heterogeneous Network-on-Chip.......................... 26 2.1 OWN Architecture.............................. 27 2.1.1 64-Core OWN Architecture: Cluster................. 28 2.1.2 1024-Core OWN Architecture: Cluster and Group......... 29 2.1.3 Intra-Group and Inter-Group Communication............ 32 2.1.4 Deadlock Free Routing........................ 33 2.2 Technology for OWN: Wireless and Optical................. 35 2.2.1 Wireless Technology......................... 35 2.2.2 Photonics Technology........................ 37 2.3 Reconfigurable-OWN (R-OWN)....................... 38 2.3.1 256-Core OWN Architecture..................... 38 2.3.2 256-Core R-OWN Architecture................... 40 2.3.3 Routing Mechanism of 256-Core R-OWN.............. 42 2.3.4 Deadlock Free Routing........................ 44 7 3 Off-Chip Interconnection Network......................... 46 3.1 On-Chip and Off-Chip Wireless Architecture................ 47 3.1.1 Metallic Interconnects (M-M-X-X)................. 49 3.1.2 Hybrid Wireless Interconnect (W/M-W/M-X-X).......... 49 3.1.2.1 On-Chip Hybrid Wireless Interconnect (W-M-X-X)... 49 3.1.2.2 Off-Chip Hybrid Wireless Interconnect (M-W-X-X)... 52 3.1.2.3 On-Chip and Off-Chip Hybrid Wireless Interconnect (W-W-X-X)........................ 52 3.2 Communication Protocol: Metallic and Hybrid Wireless Interconnect... 54 3.2.1 On-Chip Metallic and Off-Chip Metallic or Wireless Interconnects. 54 3.2.2 On-Chip Wireless Interconnects With Omnidirectional Antenna and Off-Chip Metallic Interconnects................. 56 3.2.3 On-Chip Wireless Interconnects With Directional Antenna and Off-Chip Metallic Interconnects................... 57 4 Evaluation of the Proposed Architectures...................... 58 4.1 Performance Evaluation of OWN....................... 59 4.1.1 Area Estimate............................. 59 4.1.2 Energy Estimate........................... 60 4.1.3 Saturation Throughput and Latency Comparison.......... 62 4.2 Performance Evaluation of R-OWN..................... 64 4.2.1 Area Estimation........................... 65 4.2.2 Energy Estimate........................... 66 4.2.3 Saturation Throughput and Latency Comparison.......... 67 4.3 Performance Evaluation of On-Chip and Off-Chip Wireless Network.... 70 4.3.1 Execution Time Estimate....................... 70 4.3.2 Energy per Byte Estimate...................... 71 5 Conclusions..................................... 74 References........................................ 75 8 List of Tables Table Page 2.1 Optical device parameters [1] © 2015 IEEE.................... 37 3.1 Naming convention of the baseline and proposed on-chip and off-chip wireless architectures [2].................................. 47 3.2 Summary of the baseline and proposed on-chip and off-chip wireless architec- tures [2]....................................... 53 4.1 Simulation parameters for the baseline and proposed on-chip and off-chip wireless architectures [2].............................. 71 9 List of Figures Figure Page 1.1 General purpose processor trend-line....................... 12 1.2 An example of on-chip mesh network....................... 13 1.3 Layout and physical structure with addressing of a WCube [3] © ACM DOI 10.1145/1614320.1614345............................. 18 1.4 Architecture of a small-world [4] © 2011 IEEE and a iWISE [5] network © 2011 IEEE..................................... 19 1.5 256-core Firefly architecture [6] © ACM DOI 10.1145/1555754.1555808.... 21 1.6 1024-core ATAC architecture [7] © ACM DOI 10.1145/1854273.1854332... 22 2.1 64-core OWN architecture............................. 27 2.2 Overview of a 1024-core OWN architecture [1] © 2015 IEEE.......... 29 2.3 Kilo-core OWN architecture [1] © 2015 IEEE.................. 31 2.4 Communication mechanism of a 1024-core OWN architecture [1] © 2015 IEEE. 33 2.5 Deadlock scenarios in a 1024-core OWN [1] © 2015 IEEE............ 35 2.6 256-core OWN architecture...........................