PINSTECH-168 DESIGN OF MULTICHANNEL COUNTING SYSTEM-2 FOR IBM PC AND COMPATIBLES ZAHEER AHMAD RASH ID QAMER lit NAVEED MUSHTAQ ^^ftrt' Computer Dftisioi Pakistan Institute of Nuclear Science & Technology P 0. Nilcre, Islamabad April, 2001 ABSTRACT A multichannel, Counting System 2 (MCCS-2) data acquisition plug-in card for the IBM ISA, MCA and EISA bus architecture has been designed and developed for acquisition of pulsed signal. The card features large dynamic range is achieved with the help of 16-bit pulse counters, fast signal acquisition and a self-testing capability in a single slot card. The MCCS-2 (designed by R & D group, CD) is an upgraded version of MCCS-1 [6]. The MCCS-2 consists of a plug-in interface card (MCCS-PC) for fBM PC and compatibles and a BNC- terminal module (MCCS-BNC). The MCCS-PC is address selectable and can simultaneous monitoring ten independent SCA inputs. An on board programmable timer provides elapsed time measurement. A menu-driven software program is developed for data acquisition and timer control. i TABLE OF CONTENTS DESCRIPTION PAGE Abstract i Table of contents ii List of drawings iv Introduction 1 Specifications 2 Hardware Design Description 3 3.1 Signal Isolation and Conditioning 3 3.2 Timer 3 3.3 Counter 4 3,4 Address Selectable Logic 4 3,5 Base Address Switch 5 3,6 Bus Interface 6 3.7 Status Monitoring 6 Table-1 Switch Setting 6 Tabfe-2 Addresses Table 7 PCB Fabrication 8 Installation 8 Data Acquisition Software 9 6,1 Data Acquisition 10 6.2 Data Files 11 3 Self Test 4 Analysis Conclusion & suggestions Components List References Appendix-A, The program listing LIST OF DRAWINGS No. DescfjpiLQn Page Block diagram of MCCS-2 16 Components of MCCS-2 17 MCCS-2 BNC Interface Module 18 Block diagram of the MCCS-PC interface board 19 LC. layout of the MCCS-PC interface board 20 Circuit diagram of the MCCS-PC interface board 21 PCB Artwork of MCCS-2 Component Side 22 PCB Artwork of MCCS-2 Solder Side 23 IV 1, INTRODUCTION In nuclear experiments, the signals from a detector are fed to a linear amplifier in a NIM-BIH The output of the amplifier is connected to the input of a Single Channel Analyzer (SCA). The SCA output is a loyic pulse for each event. These logic pulses are used by the counting circuitry for count rate measurement or counting events over specified period of time. For each experimental setup the data is collected and then interpreted using computer or calculator. Further, in order to determine the spatial distribution of events (for example a radiation source), similar measurements from different locations are made simultaneously. In order to ease the installation of such experiments and to improve the turn-around time, it is desired to automate the system. The Multichannel Counting System (MCCS-1) was designed by Research & Development (R & D) group of Computer Division and supplied to various division in Pakistan Institute of Nuclear Science St Technology (P1NSTECH), Institute of Nuclear Power (INUP) and Kundian Chemical Plant-I[ (KNCP-II), The Radiation & Isotopes Application Division (R1AD) and Neutron Diffraction Group ofNPD are requested for upgradation and modification of MCCS-1 system. MCCS-2 is a new designed system described in this report provides a direct interface between SCA outputs and an IBM-PC compatible compuler, capability to interface ten SCA outputs channels instead of seven and address selectable logic allows the user to interface multiple modules simultaneously connected to the computer. The interface card is designed and developed for IBM-PC/XT/AT bus. The data for multiple counting channels is stored on the computer disk along with necessary information such as elapsed time, date, number of channels etc. 1 2. SPECIFICATIONS The specifications of the MCCS-BNC module and MCCS-PC interface board; Number of input channels 10 Timer resolution 0,5nS 10 32.7 mS Max. Counts per channel 65535 (16-Bits) Time for acquisition 5 mS to 35 Minutes and 47 Sec. ISA, MCA & EISA Bus Architecture Single- I/O, Slot Interface between MCCS-PC 25 pins D-type connector and MCCS-BNC module with 26-way twisted pair ribbon cable Interface between SCA and 50 Ohm BNC connectors MCCS-PC module with Cables. 2 3- HARDWARE DESIGN DESCRIPTION MCCS-2 system consists of multichannel counting system plug-in interface card (MCCS- PC), to be installed in an IBM-PC compatibles I/O channel and BNC interface module called MCCS-BNC. The SCA oulpui pulses are terminated on MCCS-BNC interface module through a twisted pair ribbon cable are connected to the interface card within the PC. The block diagram of the overall counting system is shown in Fig 1. The SCA output is a logic pulse of 0.5u5 duration [ 1 ] for each event. These logic pulses are used by the MCCS-PC interface as input to one of its ten counting channels. A timer enables these counters for a specific period of time. The heart of the MCCS-PC card is the Intel 3253-5 programmable counter/timer I.C [2]. It contains four registers of sixteen bits each. One of which is reserved for control and remaining three registers can be used either as counters or timers independently. Four £253-5 LCs are used on a card at location U I, U2, U3 and U4, giving a total of 12 user - available registers, out of which one is used as timer and one frequency divider. The remaining ten registers perform pulse counting of the ten independent input signals. Fig. 5 shows the block diagram of the MCCS-PC board. The LC. layout of the board and the circuit diagram is shown in Fig, 5 & 6 respectively. The various sections of the design are discussed below. 3.1 SIGNAL ISOLATION* CONDITIONING The pulse width of SCA output signal is 0.5us and its range is from 0 to 6 volts. The incoming signals [6] from MCCS-BNC interface box are isolated electrically from the interface card MCCS-PC using bus isolators (RS 20B-355) to avoid probable damage to the computer from the counting system and vice versa. The output of a bus isolator is not TTL compatible as required by the computer. Hence these signals are converted to 0-5 volt using two resistor packs of Ik & 330 ohms. The output of potential dividers is fed to line receiver/driver buffers, 74LS244 (U6 & U12) for further use, 32 TIMER Not relying on the PC system clock that varies from 4.77 MHz to more than 433 MHz depending upon the make and model being used, a 2 MHZ {as basic requirement of 8253-5) crystal is used to generate basic clock for the counter/timers. A 2 MHz clock is divided by 2000 to obtain a square wave of 1 kHz, This square wave output is obtained from counter 2 of U2 that is programmed to function as divider for the incoming clock. The gate 2 of U2 is enabled permanently by pulling it up to 5 volts supply. The counter 1 3 acts as a timer in mode 0. It is loaded with an initial value in milii seconds. The gate I is enabled by software. The OUT 1 is active low until counter 1 contents are made not equal to zero. The OUT 1 signal is inverted and used to enable the gates of various counting channels. When the counter-1 is decrement to zero, the OUT 1 changes its state and disables all the counting channels. The 2 MHz clock can be divided any suitable number by software to obtain a timer resolution from 0.5 us to 32.7 mS. 3.3 COUNTER The interface has 10 counting channels. All the counters are loaded with FFFF hex initially and each counter starts in count down mode when its gate is enabled. After the specified elapsed time as discussed above, the respective gates are disabled. The counts from various channels are read by software. The present leading is subtracted from the initial value FFFF hex to find the actual events recorded by each channel 3.4 ADDRESS SELECTABLE LOGIC In MCCS-1 module has limited design features of fixed address. We faced two main problems. The first thing is that the module can be used only for seven channels with no multiple modules and secondly only one device of same address of 300Hex can be used The address selectable logic is introduced in MCCS-2 module to overcome these problems. The 3-£o-8 line decoder 74LS138 on the board serve as address decoders. One function of an address decoder is to produce a signal, which enables the peripherals for a particular address. A second related function of an address decoder is to make sure that only one device is enabled at a time to put data on bus lines. To enable address decoder, G2 signal an address selectable logic is used. Figure (3.4) shows that 8-bit Magnitude Comparators 74LS682, perform comparisons of two eight-bit binary or BCD words and provide P=Q output. In our case Qs inputs, from data switch and other inputs Px, (Address bit 5 to address bit 9 ) is from Octal Buffers/Receivers non-inverted 3-state outputs 74LS244 are feeding to 74LSG82 the P=Q output of this chip is used to enable decoders. 4 IBM PC/XT DI-D5 I/O CHANNELS DATA SWITCH > 3-8 L!NE S S-81T DECODE MAGNrrUDE P=Q COMPARATO R RS 74LS138 ADD 4-ADD9 OCTAL ADD5-ADD9 BUFFER G2 A2 74LS 682 S/LINE S- o DRIVER P A2 2 74LS244 Fig.