High Speed Signal Integrity Analysis and Differential Signaling Project Report of EE201C: Modeling of VLSI Circuits and Systems Tongtong Yu, UID: 904025158 Zhiyuan Shen, UID: 803987916 Abstract— This course project is designated for independent electric mechanism of semiconductor circuit doesn’t change study of various topics relating to VLSI modeling. In our very much, so the concentration is on the interconnects and project, the first part is an extension of the class presentation packaging. where we introduced the basic idea of signal integrity. Here we address the philosophy behind frequency domain and time The impact of to the system can be classified to signal domain. Then, we give two examples of interconnects, a critical integrity, which refers to the contamination of signal’s in- issue related to signal integrity. The second part is about tegrity due to parasitic effects of interconnects and packaging, differential signaling used in high speed application. After compared with ideal case. This may result in unsatisfactory analyzing general principles, we simulate two parallel-trace performance. For example, we design the systems for 10Gbps; transmission line, which has practical meaning in real design case. Maybe this project is not fancy, but we believe all the however, due to this effect, it can only achieve 5Gbps. Also, fundamentals provided here and those reference list in the end this may produce inaccurate logic state and even logical are the best material for everyone who wants to go further in failure. This impact can be classified in two ways this area. 1) Delay, distortion and cross-talk directly happening on We would like to express our deepest gratitude to Prof. He, for the transmission channel; his endless endeavor in and out of class. From him, we learned 2) Noise caused by grounding wire, pin connection, power how to be an independent researcher. This experience will be supply, which can be called simultaneous switching precious for our future academic life. noise (SSN). I. INTRODUCTION Traditionally, microwave circuit and high speed circuits are belonging to different subjects. But they are can be connected Recently, high speed and three dimension (3D) are the main together in the sense of “fast varying”. In microwave domain, trends of future very large scale integrated (VLSI) circuits. we study fast varying sine wave, while in high speed circuit, One feature is that the clock frequency in CMOS chip can we study fast varying pulse wave. The wave effect become reach several GHz, which has reached microwave frequency obvious when the physical size is comparable to wave length bands, and the corresponding pulses signals’ frequencies can in microwave domain; correspondingly, when the physical approach to even higher frequencies. As known to us, level size is becoming comparable to the rising time or pulse of integration has been increased due to deep sub-micro duration in digital circuits, it must be studied specifically due technology, which made system-on-chip (SoC) become possi- to wave effect. Usually, microwave circuits are analyzed in ble. Also, to realize complex systems, along with application frequency domain, while high speed circuit is analyzed in specific integrated circuits(ASIC), printed circuit board (PCB) time domain. But as the wave effect is obvious, the traditional method is still used widely. No matter what the method circuit theory are limited. For example, some elements will be mentioned above is used for our system, when the operating frequency or size dependent, which will make time domain frequency increase, all high speed systems has similar prop- solution complicated and inaccurate. In that case, we have to erties. As deep sub-micro technology develops, the size of use electromagnetic simulator, such as momentum simulator semiconductor devices and basic logic gates is very tiny, so provided by Agilent ADS to include the field effect to get an their parasitic effects is not obvious as we can still use general accurate result. circuit theory. However, when we consider those interconnects which connect different ICs within chip or within one PCB, their length, complexity and density will cause severe parasitic II. GENERAL APPROACH FOR SIGNAL INTEGRITY ISSUE effects. In the mean time, package, which are used to protect and brace the inner circuits, will cause these effects too. For As we have seen in class, Pade approximation is based on example, bonding wires, ground wires and vias can be problem moment matching. First, it expand both the original network for high speed signal propagation. As the working frequency function and Pade approximation as power series around some increase, these effects can encroach from PCB to inter-chip point in s domain. Then, equaling the coefficient with same connection and even interconnects within chips. power factor in these two series’ can determine the coefficients As a result, the high speed theory, is to investigate the elec- in both numerator and denominator. However, there is some trical property of the whole system, which consists of systems situation where moment matching theory cannot be used. interconnects, packaging and connector with semiconductor According to Appel’s theorem in complex power series theory, devices, under the action of high speed pulses. Since the power series are convergent only in the range within their convergence radius and in this range the function must be an- voltage and current along the transmission line, then according alytical. But actually, both original network function and Pade to transmission line theory, we have approximation cannot be analytical within whole frequency U = U + U (2) UWB signal in range (they both have poles), so the range of convergent radius f r is small. So, by performing Pade approximation, the final result Uf Ur I = If + Ir = − (3) may be not very accurate. Z0 Z0 For systematic description of a network’s property, we use where Z0 is the characteristic impedance. For lossless line, Synchronizedtwo Acquisition types of electric parameter. /FPGA Z0 is pure resistive. Uf and If are the voltage and current 1) The first electric parameters are voltage and current. incident wave; Ur and Ir are the voltage and current reflected The corresponding circuit’s network parameters are wave. For simplicity, we can take the normalized value, impedance, admittance and their matrix; U 2) The second electric parameters are incident wave and a = p f (4) reflected wave. The corresponding circuit’s network pa- Z0 rameters are reflection coefficients and scattering matrix. U b = p r (5) We have used the first type parameter many times as in Z0 Low-pass filter basic circuits analysis. Here we give several advantages of Then, we have the second type parameter. Threshold Signal out p U = Z0(a + b) (6) s(t)+n(t) 1) It is easy to show theDecision power transmission and matching Syncrhonization 1 condition in different part within the whole system; I = p (a − b) (7) Wideband 2 Threshold T Threshold Verify Z0 ( ) 2)Decision For arbitrary circuity,()dt there are the scattering parameters amplifier 0 Decision associated with them. They are more generalized for Also, a and b can be expressed in terms of U and I. network properties; Strobe Shift Local Phase 1 U p 3) When the frequencyPN codes is higher, the scattering parameters a = (p + Z I) (8) PulsesUWB signalRegister in Control 2 Z 0 are more easily to measure, especially for active devices; 0 1 U Time position 4)Algorithm For lossless network, the scattering matrix is unitary, p b = (p − Z0I) (9) Control Controlwhich makes it easy to obtain the relation between the 2 Z0 driving point impedance and the transmission parame- As mentioned before, a critical issue is on and off chip ters, as to make it easy to synthesize. interconnects, which can be treated as transmission line. Synchronized Acquisition a /FPGA I + Lossless III. ONE EXAMPLE USING CHARACTERISTIC METHOD IN b TIME DOMAIN ANALYSIS U Linear - Time invariant Z0 i(0,t) i(l,t) Z0 Fig. 1. Voltage, current, incident and reflected wave of one port + + + + network. u(0,t) er(l,t- ) ei(0,t- ) u(l,t) The second type parameter is no straight forward relating to - - - - the circuit elements as the first type, which is the drawback. So, as we will see later, these two types parameters are both Fig. 2. Left and right equivalent circuits for characteristic method used in analysis. Next, we will understand all of these through in time domain. an example. As shown in Fig. 1, the voltage and current of a lossless, Fig. 2 is the equivalent circuit representation for character- linear, time-invariant single port network are U and I. Take a istic method [1], which is shown on page 16 of the slides. We reference Z0 with unit of Ohms and get the following linear show an example to illustrate this method. As shown in Fig. transformation of U and I, 3, for a transmission line with impedance Z0, time delay , 2 p 3 1 Z0 assume the signal resistance and load resistance are R1 and p a 6 2 Z 2 7 U R2, respectively. The driving voltage is e(t). For t < 0, the = 6 0 p 7 (1) b 4 1 Z0 5 I value of e is zero. Also, assume all the initial conditions are p − zero. We can use the characteristic method to calculate voltage 2 Z0 2 and current along the line in time domain. Then, a and b are normalized incident wave and reflected At t=0, according to causality, we have wave. This transformation can also be interpreted from the perspective of transmission line. Assume U and I are the ei(0; −) = 0; er(l; −) = 0 (10) 2 I a + Lossless U b Linear - Time invariant UWB signal in Synchronized Acquisition /FPGA Z0 i(0,t) i(l,t) Z0 + + + + u(0,t) er(l,t- ) ei(0,t- ) u(l,t) - - - UWB signal in - R1 are mixed lumped elements, such as L,C,R at the intersection.