Philips Semiconductors Programmable Logic Devices Designing with programmable macro logic INTRODUCTION TO Because of the large number of inputs each Optimizing combinational functions in PML PROGRAMMABLE MACRO NAND gate has available, logic functions that consists largely in making choices and LOGIC DESIGN CONCEPTS require several levels of conventional 4 or 8 trade-offs. For single output logic functions, input gates may be able to be reduced to 1 or the choice is obvious from the truth table. If a Programmable Macro Logic (PML), an 2 levels. However, it is important to realize particular function’s truth table has fewer extension of the Programmable Logic Array that unlike AND-OR PLD architectures, more entries that are logical zeroes than logical (PLA) concept combines a programming or than 2 levels of logic may be implemented in ones, product of sums should be chosen and fuse array with an array of wide input NAND the PLHS501 without wasting output or input the appropriate OR-AND structure generated. gates wherein each gate folds back upon pins. Up to 72 levels of logic may be Otherwise, the usual sum of products should itself and all other such NAND gates. This is implemented due to each of the 72 foldback be chosen, minimizing as usual, before called a foldback NAND structure and its NAND gates. dropping into the two level AND-OR structure basic elements have been outlined previously (using the NAND-NAND realization). (Cavlan1, Wong2, Gheissari and Safari3). So far, the concept of a “macro” is still not Combining the availability of inversion at the evident. Two ways for the generation of a The choice of an internal NAND logic cell is input and output of the chip, the macro exist—namely, hard and soft. appropriate because the cell is functionally NAND-NAND structure can perform either Borrowing from the concept in computer complete, requiring but a single cell type to the OR-AND or the AND-OR rendition of a programming wherein a section of code generate any Boolean function. A cell within function with equal logic levels. The designer (called a macro) is repeated every time its the PLHS501 may be configured to needs only to choose the optimal rendition to use is required, we can establish accommodate from one to 32 inputs from the suit his needs (see Table 1). Truth tables with subfunctions which can be repeated each outside world, and up to 72 inputs from within 50% ones can use either version at the time required. The user defined or soft macro the chip. Because the user can select either designers whim unless other uses arise. can be one which will generate a function by direct or inverted input variables, and either a fused interconnect. When a fixed design direct or complemented output, the NAND function is provided, it is a hard macro. This function can generate, with a single pass may be an optimized structure like a flip-flop PERFORMANCE through the programming array, the basic or an adder, or some other function which is The PLHS501 (Figure 2) is a high speed, four logic functions of AND, OR, NAND, generated on the foundation, by the oxide isolated, vertically fused PML device NOR. all these basic functions, can be manufacturer. Soft macros are seldom containing 72 internal NAND functions which extremely wide, of course (see Figure 1). optimized or precisely consistent, but hard are combined with 24 dedicated outputs. A This convenient structure allows efficient macros are both optimized and unalterable. large collection of applications, both exploitation of all widely used minimization combinational and sequential, may be techniques (Karnaugh Maps, When a user function for a particular use is configured using this part which looks roughly Quine-McClusky, Boolean Algebra, etc.). isolated, defined and repetition of the function like a small, user definable gate array. For the is required, special software constructs are The obvious extensions to additional sake of clarity, worst case passing a signal provided which will allow it to be defined at a from an input, making one pass through the combinational functions for decoding, higher performance and functional density, multiplexing and general Boolean functions is NAND array (output terms) and exiting an and an array of choices which contain output takes around 25 nanoseconds with straightforward. Adding feedback to the optimized functions or hard macros will be system expands the range of realizable each incremental pass through the NAND offered in successor chips. In particular, the foldback array taking about 8 nanoseconds. functions to include sequential as well as PML2552 and PML2852 include an array of combinational functions. Figure 2 illustrates flip-flops for state machine design. the basic arrangement of the PLHS501. A A A + B + . + Z IA A B (OR) Z A B AB . Z IB B B (NAND) Z A Z A + B + . + Z IZ Z B (NOR) Z A AB . Z B (AND) Z INPUT NAND ARRAY OUTPUT SECTION SECTION Figure 1. PML Basic Functions November 1993 1 Philips Semiconductors Programmable Logic Devices Designing with programmable macro logic Table 1. Example Demonstration F1 (A, B, C) = ABC + ABC + ABC + ABC + ABC A B C f1 C AB 00 01 11 10 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 The optimal choice would be to generate 1 0 1 1 the zero entries 1 1 0 1 1 1 1 1 If we group on the one entries we shall get: AB +BC + BC A A IA A B B B IB B F (A, B, C) C 1 C COST = 4 INTERNAL GATES B AND 9 INPUTS IC C C INPUTS NAND ARRAY OUTPUT If we group on the zero entries we get instead: F1 = (B + C) (A + B + C) A IA A B B IB B C F (A, B, C) C 1 A IC C B COST = 3 INTERNAL GATES C AND 7 INPUTS INPUTS NAND ARRAY OUTPUT November 1993 2 Philips Semiconductors Programmable Logic Devices Designing with programmable macro logic INPUT 71 0 BUFFERS I0 OUTPUT I23 72 INPUT BUFFERS NAND TERMS TERMS x2 x2 x2 x2 x2 x2 x4 x4 x4 x4 x4 x4 x4 x4 B0 – B3 x4 B4 – B7 x4 x4 X0, X2, X4, X6 x4 X1, X3, X5, X7 x2 O0, O2 x2 O1, O3 x2 O4, O6 x2 O5, O7 OUTPUT Figure 2. PLHS501 Logic Diagram BUFFERS November 1993 3 Philips Semiconductors Programmable Logic Devices Designing with programmable macro logic The data sheet first lists some maximum It is intriguing that subtracting one from the less of a delay than the other, and since the propagation delays from an input, through a other yields a NAND foldback gate delay of 5 individual rise and fall delays are not NAND output term and out through various to 6ns when the worst case gate delay of an specified, this causes the apparent output gates. Secondly, it lists maximum internal foldback gate is listed as 8ns. This is discrepancy between the two delays. propagation delays from an input, through a due to the fact that a gate has less of a delay Figure 3, Figure 4, Figure 5 and Figure 6 NAND foldback term, through a NAND output when its output is falling (t ) than when its PHL show graphically the timing paths listed in the term and out through the different output output is rising (t ). When passing a signal PLH PLHS501 data sheet. gates. through two NAND gates one gate will have PLHS501 TIMING tPD INPUT 71 0 BUFFERS I0 OUTPUT I23 72 INPUT BUFFERS NAND TERMS TERMS x2 x2 x2 x2 x2 x2 x4 x4 x4 x4 x4 x4 x4 x4 B0 – B3 x4 B4 – B7 x4 x4 X0, X2, X4, X6 x4 X1, X3, X5, X7 x2 O0, O2 x2 O1, O3 tPD x2 O4, O6 NOTE: x2 O , O tPD = 22ns maximum. 5 7 Input Buffer + 1 NAND gate + Output Buffer (O, /O,B). OUTPUT BUFFERS Figure 3. tPD –22ns Maximum November 1993 4 Philips Semiconductors Programmable Logic Devices Designing with programmable macro logic PLHS501 TIMING (Continued) tPD INPUT 71 0 BUFFERS I0 OUTPUT I23 72 INPUT BUFFERS NAND TERMS TERMS x2 x2 x2 x2 x2 x2 x4 x4 x4 x4 x4 x4 x4 x4 B0 – B3 x4 B – B x4 4 7 tPD x4 X0, X2, X4, X6 x4 X1, X3, X5, X7 x2 O0, O2 x2 O1, O3 x2 NOTE: O4, O6 t = 30ns maximum. PD x2 Input Buffer + 2 NAND gates + XOR gate + Output Buffer O5, O7 OUTPUT BUFFERS Figure 4. tPD –30ns Maximum November 1993 5 Philips Semiconductors Programmable Logic Devices Designing with programmable macro logic PLHS501 TIMING (Continued) tPD INPUT 71 0 BUFFERS I0 OUTPUT I23 72 INPUT BUFFERS NAND TERMS TERMS x2 x2 x2 x2 x2 x2 x4 x4 x4 x4 x4 x4 x4 x4 B0 – B3 x4 B – B x4 4 7 tPD x4 X0, X2, X4, X6 x4 X1, X3, X5, X7 x2 O0, O2 x2 O1, O3 NOTE: x2 O4, O6 tPD = 25ns maximum. Input Buffer + 1 NAND gate + XOR gate + Output Buffer x2 O5, O7 OUTPUT BUFFERS Figure 5. tPD –25ns Maximum November 1993 6 Philips Semiconductors Programmable Logic Devices Designing with programmable macro logic PLHS501 TIMING (Continued) tPD INPUT 71 0 BUFFERS I0 OUTPUT I23 72 INPUT BUFFERS NAND TERMS TERMS tPD x2 x2 x2 x2 x2 x2 x4 x4 x4 x4 x4 x4 x4 x4 B0 – B3 x4 B4 – B7 x4 x4 X0, X2, X4, X6 x4 X1, X3, X5, X7 x2 O0, O2 x2 O1, O3 x2 O , O NOTE: 4 6 tPD = 8ns maximum.