Embedded Intel486™ Processor Hardware Reference Manual Release Date: July 1997 Order Number: 273025-001 The embedded Intel486™ processors may contain design defects known as errata which may cause the products to deviate from published specifications. Currently characterized errata are available on request. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or oth- erwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 or visit Intel’s web site at http:\\www.intel.com Copyright © INTEL CORPORATION, July 1997 *Third-party brands and names are the property of their respective owners. CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS ................................................................................................... 1-1 1.2 NOTATIONAL CONVENTIONS..................................................................................... 1-3 1.3 SPECIAL TERMINOLOGY ............................................................................................ 1-4 1.4 ELECTRONIC SUPPORT SYSTEMS ........................................................................... 1-5 1.4.1 FaxBack Service ........................................................................................................1-5 1.4.2 World Wide Web ........................................................................................................1-5 1.5 TECHNICAL SUPPORT ................................................................................................ 1-5 1.6 PRODUCT LITERATURE.............................................................................................. 1-6 1.6.1 Related Documents ...................................................................................................1-6 CHAPTER 2 INTRODUCTION 2.1 PROCESSOR FEATURES............................................................................................ 2-2 2.2 Intel486™ PROCESSOR PRODUCT FAMILY.............................................................. 2-4 2.2.1 Operating Modes and Compatibility...........................................................................2-5 2.2.2 Memory Management ................................................................................................2-5 2.2.3 On-chip Cache ...........................................................................................................2-6 2.2.4 Floating-Point Unit .....................................................................................................2-6 2.2.5 Upgrade Power Down Mode......................................................................................2-7 2.3 SYSTEM COMPONENTS ............................................................................................. 2-7 2.4 SYSTEM ARCHITECTURE ........................................................................................... 2-7 2.4.1 Single Processor System...........................................................................................2-8 2.4.2 Loosely Coupled Multi-Processor System .................................................................2-9 2.4.3 External Cache ........................................................................................................2-10 2.5 SYSTEMS APPLICATIONS......................................................................................... 2-11 2.5.1 Embedded Personal Computers..............................................................................2-12 2.5.2 Embedded Controllers .............................................................................................2-12 iii EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL CHAPTER 3 INTERNAL ARCHITECTURE 3.1 INSTRUCTION PIPELINING ......................................................................................... 3-6 3.2 BUS INTERFACE UNIT................................................................................................. 3-7 3.2.1 Data Transfers ...........................................................................................................3-8 3.2.2 Write Buffers ..............................................................................................................3-8 3.2.3 Locked Cycles............................................................................................................3-9 3.2.4 I/O Transfers ..............................................................................................................3-9 3.3 CACHE UNIT............................................................................................................... 3-10 3.3.1 Cache Structure .......................................................................................................3-10 3.3.2 Cache Updating .......................................................................................................3-12 3.3.3 Cache Replacement ................................................................................................3-12 3.3.4 Cache Configuration ................................................................................................3-12 3.4 INSTRUCTION PREFETCH UNIT............................................................................... 3-13 3.5 INSTRUCTION DECODE UNIT................................................................................... 3-14 3.6 CONTROL UNIT.......................................................................................................... 3-14 3.7 INTEGER (DATAPATH) UNIT..................................................................................... 3-14 3.8 FLOATING-POINT UNIT ............................................................................................. 3-15 3.8.1 IntelDX2™ and IntelDX4™ Processor On-Chip Floating-Point Unit ........................3-15 3.9 SEGMENTATION UNIT............................................................................................... 3-15 3.10 PAGING UNIT ............................................................................................................. 3-16 CHAPTER 4 BUS OPERATION 4.1 DATA TRANSFER MECHANISM.................................................................................. 4-1 4.1.1 Memory and I/O Spaces ............................................................................................4-1 4.1.1.1 Memory and I/O Space Organization....................................................................4-2 4.1.2 Dynamic Data Bus Sizing ..........................................................................................4-3 4.1.3 Interfacing with 8-, 16-, and 32-Bit Memories ............................................................4-5 4.1.4 Dynamic Bus Sizing During Cache Line Fills .............................................................4-9 4.1.5 Operand Alignment ..................................................................................................4-10 4.2 BUS ARBITRATION LOGIC ........................................................................................ 4-12 4.3 BUS FUNCTIONAL DESCRIPTION............................................................................ 4-15 4.3.1 Non-Cacheable Non-Burst Single Cycle..................................................................4-16 4.3.1.1 No Wait States ....................................................................................................4-16 4.3.1.2 Inserting Wait States ...........................................................................................4-17 4.3.2 Multiple and Burst Cycle Bus Transfers...................................................................4-17 4.3.2.1 Burst Cycles ........................................................................................................4-18 4.3.2.2 Terminating Multiple and Burst Cycle Transfers .................................................4-19 4.3.2.3 Non-Cacheable, Non-Burst, Multiple Cycle Transfers.........................................4-19 4.3.2.4 Non-Cacheable Burst Cycles ..............................................................................4-20 4.3.3 Cacheable Cycles ....................................................................................................4-21 4.3.3.1 Byte Enables during a Cache Line Fill ................................................................4-22 iv CONTENTS 4.3.3.2 Non-Burst Cacheable Cycles ..............................................................................4-23 4.3.3.3 Burst Cacheable Cycles......................................................................................4-24 4.3.3.4