SPEC CPU2017: PERFORMANCE, ENERGY AND EVENT CHARACTERIZATION ON MODERN PROCESSORS by RANJAN HEBBAR SEETHUR RAVIRAJ A THESIS Submitted in partial fulfillment of the requirements for the degree of Master of Science in Engineering in The Department of Electrical & Computer Engineering to The School of Graduate Studies of The University of Alabama in Huntsville HUNTSVILLE, ALABAMA 2018 In presenting this thesis in partial fulfillment of the requirements for a master’s de- gree from The University of Alabama in Huntsville, I agree that the Library of this University shall make it freely available for inspection. I further agree that permis- sion for extensive copying for scholarly purposes may be granted by my advisor or, in his/her absence, by the Chair of the Department or the Dean of the School of Graduate Studies. It is also understood that due recognition shall be given to me and to The University of Alabama in Huntsville in any scholarly use which may be made of any material in this thesis. (student signature) (date) ii THESIS APPROVAL FORM Submitted by Ranjan Hebbar Seethur Raviraj in partial fulfillment of the require- ments for the degree of Master of Science in Engineering in Computer Engineering and accepted on behalf of the Faculty of the School of Graduate Studies by the thesis committee. We, the undersigned members of the Graduate Faculty of The University of Alabama in Huntsville, certify that we have advised and/or supervised the candidate on the work described in this thesis. We further certify that we have reviewed the thesis manuscript and approve it in partial fulfillment of the requirements for the degree of Master of Science in Engineering in Computer Engineering. Committee Chair (Dr. Aleksandar Milenkovic) (date) (Dr. Rhonda Gaede) (date) (Dr. B. Earl Wells) (date) Department Chair (Dr. Ravi Gorur) (date) College Dean (Dr. Shankar Mahalingam) (date) Graduate Dean (Dr. David Berkowitz) (date) iii ABSTRACT The School of Graduate Studies The University of Alabama in Huntsville Degree Master of Science in Engineering College/Dept. Engineering/Electrical & Computer Engineering Name of Candidate Ranjan Hebbar Seethur Raviraj Title SPEC 2017: Performance, Energy and Event Characterization on Modern Processors Computer engineers in both academia and industry rely on a standardized set of benchmarks to quantitatively evaluate the performance of modern computer systems and research prototypes. The SPEC CPU2017 benchmark suites are the most recent incarnation of standard benchmarks designed to stress a system’s processor, memory subsystem, and compiler. This thesis describes the results of measurement-based studies focusing on performance and energy-efficiency of modern Intel processors us- ing SPEC CPU2017. The studies utilize SPEC CPU2017 run utilities as well as mod- ern Linux tools for profiling that interface on-chip performance monitoring units. The thesis encompasses the following aspects of performance evaluation: (a) top-view char- acterization of individual benchmarks; (b) analysis of scalability in the context of speed and throughput metrics, while varying the number of threads for speed bench- marks and copies for rate benchmarks, respectively; (c) analysis using Intel’s Top- down Microarchitectural Analysis Method, (d) comparative performance study of dif- ferent computers with Intel’s Core i7 and Xeon processors, and (e) analysis of perfor- mance impact of hardware prefetching in modern processors. Abstract Approval: Committee Chair Department Chair Graduate Dean iv ACKNOWLEDGMENTS The work presented in this thesis would be incomplete without thanking all the people who helped me directly and indirectly. First, I would like to express my sincere gratitude to my advisor, Dr. Aleksandar Milenkovic for his constant support at every stage of this work for creating an inspirational work environment in the LaCASA laboratory. He inspired me personally and professionally with his patience and his interest towards student learning. I will be always grateful to Dr. Ravi Gorur, Chair of the Electrical and Com- puter Engineering Department, for encouraging me to pursue my thesis studies, and for providing me with financial support through the teaching assistantship during Fall-2017, Spring-2018 and Summer-2018 semesters. I would like to thank Mrs. Mounika Ponugoti, Mr. Prawar Poudel and Dr. Ar- men Dzhagaryan for their constant support and for helping me to get started in the laboratory. I would like to thank Dr. Rhonda Gaede and Dr. Buren Wells for teaching me valuable skills and serving on my committee. I would also like to thank all the profes- sors and staff members who helped me during my time at the University of Alabama in Huntsville. Finally, I would like to express my deepest gratitude to my parents, Raviraj Hebbar and Jyothi Hebbar, for their unconditional love and support. I would like to thank my grandparents, Subramanya T S and Jayashree T S, for providing continuous support and encouragement for higher studies. v Dedicated to the memory of my grandmother, T S Jayashree, who will forever be in our hearts. vi TABLE OF CONTENTS Page LIST OF FIGURES.…………………………………………………………………………..ix LIST OF TABLES.…………………………………………………………………………....xii CHAPTER CHAPTER 1 INTRODUCTION ................................................................................. 1 1.1 Background and Motivation ........................................................................... 1 1.2 Scope of This Thesis ........................................................................................ 3 1.3 Contributions .................................................................................................. 5 1.4 Findings .......................................................................................................... 5 1.5 Outline ............................................................................................................ 7 CHAPTER 2 SPEC CPU2017 .................................................................................... 8 2.1 Background ..................................................................................................... 8 2.2 History and Evolution of SPEC CPU ............................................................10 2.3 CPU2017 ........................................................................................................12 CHAPTER 3 TEST ENVIRONMENT & PROFILING TOOLS ...............................18 3.1 Experimental Goals .......................................................................................18 3.2 Intel Microarchitectures: An Overview .........................................................19 3.2.1 Intel Ivy Bridge .......................................................................................21 3.2.2 Intel Haswell Microarchitecture ............................................................30 3.2.3 Intel Skylake Microarchitecture .............................................................33 3.2.4 Intel Kaby Lake ......................................................................................36 3.2.5 Intel Coffee Lake .....................................................................................36 3.3 Systems under Test .......................................................................................38 3.4 Tools and Applications ...................................................................................41 vii 3.4.1 Linux perf ................................................................................................41 3.4.2 Likwid .....................................................................................................44 3.4.3 Intel VTune Amplifier ............................................................................45 CHAPTER 4 BASELINE SPEC EVALUATION ......................................................49 4.1 Top-down Microarchitectural Analysis Method ............................................49 4.2 Thread Affinity ..............................................................................................53 4.3 Baseline Evaluation .......................................................................................56 4.3.1 SPEC CPU2017 Speed Benchmark Suites .............................................57 4.3.2 SPEC CPU2017 Rate Benchmark Suites ...............................................60 CHAPTER 5 SPEC CPU2017 BENCHMARKS CHARACTERIZATION ...............63 5.1 SPEC CPU2017 Speed Benchmarks Characterization .................................64 5.1.1 General View of Benchmarks .................................................................64 5.1.2 Control-Flow Instructions and Branch Prediction Accuracy .................67 5.1.3 Cache Hierarchy .....................................................................................69 5.1.4 Top-down Microarchitectural Analysis Method Results ........................71 5.1.5 Clock Rates, Energy, and Power ............................................................76 5.2 SPEC CPU2017 Rate Benchmarks Characterization ...................................79 5.2.1 General View of Benchmarks .................................................................79 5.2.2 Control-Flow Instructions and Branch Prediction Accuracy .................82 5.2.3 Cache Hierarchy .....................................................................................84 5.2.4 Top-down Microarchitectural Analysis Method Results ........................86 5.2.5 Clock Rates, Energy, and Power ............................................................92