Title Page PowerPC Microprocessor Family: Vector/SIMD Multimedia Extension Technology Programming Environments Manual Version 2.06 August 22, 2005 ® Copyright and Disclaimer © Copyright International Business Machines Corporation 1998, 2003, 2004, 2005 All Rights Reserved Printed in the United States of America August-2005 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both. IBM IBM Logo PowerPC PowerPC Architecture Java and all Java-based trademarks are trademarks of Sun Microsystems, Inc. in the United States, other countries, or both. Other company, product, and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. 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IBM Systems and Technology Group 2070 Route 52, Bldg. 330 Hopewell Junction, NY 12533-6351 The IBM home page can be found at ibm.com The IBM semiconductor solutions home page can be found ibm.com/chips vector_simd_pem_title.fm.2.06 August 22, 2005 Programming Environments Manual Vector/SIMD Multimedia Extension Technology Contents Contents ......................................................................................................................... 3 List of Tables .................................................................................................................. 7 List of Figures ................................................................................................................ 9 About This Book .......................................................................................................... 15 Audience ............................................................................................................................................... 16 Organization .......................................................................................................................................... 16 Suggested Reading ............................................................................................................................... 17 General Information .............................................................................................................................. 17 PowerPC Documentation ...................................................................................................................... 17 Conventions .......................................................................................................................................... 19 Acronyms and Abbreviations ................................................................................................................ 20 Terminology Conventions ..................................................................................................................... 22 1. Overview .................................................................................................................... 23 1.1 Vector Processing Technology Overview ....................................................................................... 25 1.1.1 64-Bit Vector Processing Technology and the 32-Bit Subset ................................................ 26 1.1.2 Levels of the Vector ISA ........................................................................................................ 26 1.1.3 Features Not Defined by the Vector ISA ............................................................................... 27 1.2 Vector Processing Architectural Model ........................................................................................... 27 1.2.1 Vector Registers and Programming Model ............................................................................ 27 1.2.2 Operand Conventions ............................................................................................................ 28 1.2.2.1 Byte Ordering ................................................................................................................. 28 1.2.2.2 Floating-Point Conventions ............................................................................................ 29 1.2.3 Vector Addressing Modes ..................................................................................................... 30 1.2.4 Vector Instruction Set ............................................................................................................ 31 1.2.5 Vector Cache Model .............................................................................................................. 32 1.2.6 Vector Exception Model ......................................................................................................... 32 1.2.7 Memory Management Model ................................................................................................. 32 2. Vector Register Set ................................................................................................... 33 2.1 Overview of the Vector and PowerPC Registers ............................................................................ 33 2.2 Registers Defined by Vector ISA ..................................................................................................... 35 2.2.1 Vector Register File (VRF) .................................................................................................... 35 2.2.2 Vector Status and Control Register (VSCR) .......................................................................... 36 2.2.3 VRSAVE Register (VRSAVE) ................................................................................................ 38 2.3 Additions to the PowerPC UISA Registers ...................................................................................... 39 2.3.1 PowerPC Condition Register ................................................................................................. 39 2.4 Additions to the PowerPC OEA Registers ...................................................................................... 40 2.4.1 VPU Bit in the PowerPC Machine State Register (MSR) ...................................................... 40 2.4.2 Machine Status Save/Restore Registers (SRR) .................................................................... 41 2.4.2.1 Machine Status Save/Restore Register 0 (SRR0) ......................................................... 41 2.4.2.2 Machine Status Save/Restore Register 1 (SRR1) ......................................................... 42 vector_simd_pemTOC.fm.2.06 Contents August 22, 2005 Page 3 of 317 Programming Environments Manual Vector/SIMD Multimedia Extension Technology 3. Operand Conventions ............................................................................................... 43 3.1 Data Organization in Memory .......................................................................................................... 43 3.1.1 Aligned and Misaligned Accesses ......................................................................................... 43 3.1.2 VPU Byte Ordering ................................................................................................................ 44 3.1.2.1 Big-Endian Byte Ordering ............................................................................................... 44 3.1.2.2 Little-Endian Byte Ordering ............................................................................................ 44 3.1.3 Quadword Byte Ordering Example ........................................................................................ 45 3.1.4 Aligned Scalars in Little-Endian Mode ................................................................................... 46 3.1.5 Vector Register and Memory Access Alignment .................................................................... 48 3.1.6 Quadword Data Alignment ..................................................................................................... 48 3.1.6.1 Accessing a Misaligned Quadword in Big-Endian Mode ................................................ 49 3.1.6.2 Accessing a Misaligned Quadword in Little-Endian Mode .............................................. 51 3.1.6.3 Scalar Loads and Stores ................................................................................................ 52 3.1.6.4 Misaligned Scalar Loads and Stores .............................................................................. 52 3.1.7 Mixed-Endian Systems .......................................................................................................... 52 3.2 Vector Floating-Point Instructions—UISA ....................................................................................... 53 3.2.1 Floating-Point