ST7LUS5, ST7LU05, ST7LU09 8-bit low cost, low pin-count MCU for automotive, with single voltage Flash memory, ADC, timers Features Memories ■ 1 to 2 Kbytes single voltage Flash program memory with readout protection, in-circuit and in-application programming (ICP and IAP), 10k write/erase cycles guaranteed, data retention SO8 150-mil (1) 20 years ■ 128 bytes RAM ■ Up to 128 bytes data EEPROM, 300k 2 timers write/erase cycles guaranteed, data retention 20 years ■ One 8-bit lite timer with prescaler including: watchdog, 1 real-time base and 1 input capture Clock, reset and supply management ■ One 12-bit auto-reload timer with output ■ Internal low voltage supervisor (LVD) for compare function and PWM reliable power-on/-off start-up procedures A/D converter ■ Clock sources: Internal trimmable 8 MHz RC ■ oscillator, internal low power, low frequency 10-bit resolution for 0 to VDD RC oscillator or external clock ■ 5 input channels ■ 5 power saving modes: Halt, auto wake-up from halt, active halt, wait and slow Instruction set Interrupt management ■ 8-bit data manipulation ■ ■ 11 interrupt vectors plus TRAP and reset 63 basic instructions with illegal opcode detection ■ 5 external interrupt lines (on 5 vectors) ■ 17 main addressing modes I/O ports ■ 8 x 8 unsigned multiply instruction ■ 5 multifunctional bidirectional I/O lines Development tools ■ 1 additional output line ■ Full hardware/software development package ■ 6 alternate function lines ■ Debug module ■ 5 high sink outputs Table 1. Device summary ObsoleteFlash program Product(s) - ObsoleteOperating Product(s) CPU Operating Device RAM/EEPROM Peripherals memory voltage frequency temp. ObsoleteST7LUS5 1 Kbyte Product(s) - ObsoleteLite timer with Product(s) 128 bytes RAM/no EEPROM watchdog, -40°C to ST7LU05 3.0V to 5.5V auto-reload Up to 8 +85°C/ @ f = 8 timer with 1 CPU MHz RC -40°C to 2 Kbytes 128 bytes RAM/128 bytes MHz ST7LU09 PWM, 125°C EEPROM 10-bit ADC 1. DIP16 package available for development or tool prototyping purposes only. Not orderable in production quantities. February 2008 Rev 3 1/124 www.st.com 1 Contents ST7LUS5, ST7LU05, ST7LU09 Contents 1 Description . 11 2 Package pinout and device pin description . 12 3 Register and memory map . 14 4 Flash program memory . 18 4.1 Introduction . 18 4.2 Main features . 18 4.3 Programming modes . 18 4.3.1 In-circuit programming (ICP) . 18 4.3.2 In-application programming (IAP) . 19 4.4 ICC interface . 19 4.5 Memory protection . 21 4.5.1 Readout protection . 21 4.5.2 Flash write/erase protection . 21 4.6 Register description . 22 4.6.1 Flash control/status register (FCSR) . 22 5 Central processing unit . 23 5.1 Introduction . 23 5.2 Main features . 23 5.3 CPU registers . 23 5.3.1 Accumulator (A) . 23 5.3.2 Index registers (X and Y) . 23 5.3.3 Program counter (PC) . 23 Obsolete Product(s)5.3.4 Condition code register - Obsolete (CC) . Product(s). 24 5.3.5 Stack pointer (SP) . 26 Obsolete Product(s) - Obsolete Product(s) 6 Supply, reset and clock management . 27 6.1 Internal RC oscillator adjustment . 27 6.2 Register description . 29 6.2.1 Main clock control/status register (MCCSR) . 29 6.2.2 RC control register (RCCR) . 29 2/124 ST7LUS5, ST7LU05, ST7LU09 Contents 6.2.3 System integrity (SI) control/status register (SICSR) . 30 6.2.4 Internal RC prescaler selection register (INTRCPRR) . 30 6.2.5 Clock controller control/status register (CKCNTCSR) . 31 6.3 Reset sequence manager (RSM) . 33 6.3.1 Introduction . 33 6.3.2 Asynchronous external RESET pin . 34 6.3.3 External power-on reset . 34 6.3.4 Internal low voltage detector (LVD) reset . 34 6.3.5 Internal watchdog reset . 34 6.4 Register description . 36 6.4.1 Multiplexed I/O reset control register 1 (MUXCR1) . 36 6.4.2 Multiplexed I/O reset control register 0 (MUXCR0) . 36 7 Interrupts . 37 7.1 Non-maskable software interrupt . 37 7.2 External interrupts . 38 7.3 Peripheral interrupts . 38 7.3.1 External interrupt control register 1 (EICR1) . 41 7.3.2 External interrupt control register 2 (EICR2) . 41 7.4 System integrity management (SI) . 42 7.4.1 Low voltage detector (LVD) . 42 7.4.2 SI register description . 44 8 Power saving modes . 45 8.1 Introduction . 45 8.2 Slow mode . 45 8.3 Wait mode . 46 8.4 Active halt and halt modes . 47 8.4.1 Active halt mode . 48 Obsolete Product(s)8.4.2 Halt mode . .- . Obsolete. Product(s). 49 8.5 Auto wake-up from halt mode . 52 Obsolete 8.5.1Product(s) Register description - .Obsolete . .Product(s) . 55 9 I/O ports . 57 9.1 Introduction . 57 9.2 Functional description . 57 3/124 Contents ST7LUS5, ST7LU05, ST7LU09 9.2.1 Input modes . 57 9.2.2 Output modes . 58 9.2.3 Alternate functions . 59 9.3 Unused I/O pins . 61 9.4 Low power modes . 61 9.5 Interrupts . 61 9.6 I/O port implementation . 62 10 On-chip peripherals . 63 10.1 Lite timer . 63 10.1.1 Introduction . 63 10.1.2 Main features . 63 10.1.3 Functional description . 64 10.1.4 Low power modes . 66 10.1.5 Interrupts . 66 10.1.6 Register description . ..