Worcester Polytechnic Institute Pre-Silicon Verification of Tegra Image Signal Processor Major Qualifying Project Naumaan Ansari | Stephen Lee | Zhongjie Wu Submitted To Tony Cheng Yunqing Chen Gurdeepak Grewal Rupesh Shah Advisor Andrew Klein 3/8/2012 [Some materials have been removed due to confidentiality] AUTHORSHIP Section Author Abstract Zhongjie Wu Executive Summary Naumaan Ansari 1.0 Introduction Stephen Lee 2.0 Background 2.1 NVIDIA Corporation All 2.2 ASIC Design Zhongjie Wu 2.3 Tegra ISP Architecture Naumaan Ansari 2.4 CSI Stephen Lee 2.5 Video Input Zhongjie Wu 2.6 Image Signal Processor Zhongjie Wu 3.0 Power Verification Naumaan Ansari 4.0 CSI Code Coverage Testing Stephen Lee 5.0 Register Initial Value Test Zhongjie Wu 6.0 Random Test for FX Subunit Zhongjie Wu i TABLE OF CONTENTS Authorship ................................................................................................................................................................ i List of Figures ........................................................................................................................................................ iv List of Tables .......................................................................................................................................................... iv Abstract ..................................................................................................................................................................... v Executive summary ............................................................................................................................................. vi Nomenclature ..................................................................................................................................................... viii 1.0 Introduction ............................................................................................................................................... 1 2.0 Background ................................................................................................................................................ 3 2.1 NVIDIA Corporation and Tegra ...................................................................................................... 3 2.2 ASIC Design and Verification Basics ............................................................................................. 5 2.3 Tegra ISP Architecture Overview .................................................................................................. 8 2.4 Camera Serial Interface ..................................................................................................................... 8 2.5 Video Input .......................................................................................................................................... 10 2.6 Image Signal Processor .................................................................................................................. 10 2.6.1 Overview ..................................................................................................................................... 10 2.6.2 The FX Subunit .......................................................................................................................... 13 3.0 Power Verification ................................................................................................................................ 13 3.1 Introduction ........................................................................................................................................ 13 3.2 Important Concepts ......................................................................................................................... 14 3.2.1 RTL (Register-Transfer Level) ............................................................................................ 14 3.2.2 RTAPI (RunTest Application Programming Interface) ............................................. 14 3.2.3 Clock Gating ............................................................................................................................... 14 3.2.4 Power Verification ................................................................................................................... 14 3.3 Methodology ....................................................................................................................................... 16 3.3.1 Introduction ............................................................................................................................... 16 3.3.2 ISP/CSI/VI Power Verification ........................................................................................... 16 3.3.3 Test Cases ................................................................................................................................... 16 3.3.4 Power Flow ................................................................................................................................ 17 3.4 Results ................................................................................................................................................... 19 3.4.1 Power Test Code ...................................................................................................................... 19 3.4.2 Power Report ............................................................................................................................ 21 3.5 Summary .............................................................................................................................................. 22 4.0 CSI Code Coverage Testing ................................................................................................................ 23 4.1 Introduction ........................................................................................................................................ 23 4.2 Important Concepts ......................................................................................................................... 23 4.2.1 Verdi .............................................................................................................................................. 23 4.2.2 Code Coverage ........................................................................................................................... 23 4.2.3 VCS Pragmas .............................................................................................................................. 25 4.3 Methodology ....................................................................................................................................... 25 4.3.1 Code Coverage ........................................................................................................................... 25 4.3.2 VCS Pragmas .............................................................................................................................. 27 4.4 Results ................................................................................................................................................... 28 4.5 Summary .............................................................................................................................................. 29 ii 5.0 Register Initial Value Tests ............................................................................................................... 30 5.1 Introduction ........................................................................................................................................ 30 5.2 Important Concepts ......................................................................................................................... 30 5.2.1 Register Read and Write Test ............................................................................................. 30 5.2.2 Specification Files .................................................................................................................... 30 5.2.3 The Host1xClassGen.pl Script and related files ............................................................ 30 5.3 Methodology ....................................................................................................................................... 31 5.4 Results ................................................................................................................................................... 33 5.4.1 Modification of Perl Script .................................................................................................... 33 5.4.2 Generated Tests ........................................................................................................................ 34 5.5 Summary ................................................................................... Error! Bookmark not defined. 6.0 Random Test for FX Subunit ............................................................................................................. 34 6.1 Introduction ........................................................................................................................................ 35 6.2 Important Concepts ......................................................................................................................... 35 6.2.1 The FX Subunit .......................................................................................................................... 35 6.2.2 Testbench ...................................................................................................................................